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Does ECC Error Detection should be disabled during Flash Programming?

Pashan None
Genius 5660 points


Hello Support,

Attached is a snapshot from spna117a.pdf [F035 130nm Device] which mentions that ECC Error Detection/Reporting shall be disabled inside Cortex-R4 Core as well as inside Flash Wrapper during Flash Programming.
Is that valid for Bank 0 as well as Bank 7 Programming for F021 65nm device and if so why?

Thank you.
Regards
Pashan

  • 0
    TI__Guru 68980 points

    Pashan,

    There is a similar comment in the F021 Flash API Reference Guide:

    The wording is a little weaker I think because we now have a part (not available as a catalog product) where the ECC cannot be disabled, and this causes issue with Blank-Check as noted when it talks about 'L2FMC'.  In other words, since erased flash will have a bad ECC it's easier if you turn ECC off during these operations. 

    -Anthony

  • 0 in reply to Anthony F. Seely
    Genius 5660 points

    Hello Anthony,

    Thank you for the answer.
    I understood now that Blank Check will have the possibility of failure when ECC is enabled.

    Question is does PROGRAMMING of Flash Cell [Bank 0 or Bank 7 (FLEE)] depends in any way when ECC is enabled within Cortex-R4 core and inside Flash Wrapper?

    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Guru 68980 points

    Pashan,

    No, the ECC in the flash has to be explicitly programmed, and it appears in a different space in the memory map.

    It's totally different than the SRAM where a valid syndrome is written back to memory in parallel with the data write by the CPU's logic.

    -Anthony

  • 0 in reply to Anthony F. Seely
    TI__Genius 9015 points

    Pashan,

    F021 is different from F035 in that the ECC values can be written at the same time as the data, whereas in F035 it would take 3 programming commands to write the 64 bits of data and its corresponding ECC.  Therefore, erased memory is the only problematic operation that could cause ECC errors when read.