Other Parts Discussed in Thread: HALCOGEN
Hi,
I am using MIBSPI1 of TMS570LS1113 controller for SPI data transfer. Basic driver i have developed for General SPI & SPI using DMS without enabling Multibuffer mode. I have enabled the loopback mode for testing purpose
While testing i have observed that in General SPI mode whatever the data i am sending its getting loop backed. But in SPI with DMA i am getting the problem.
This is the buffer from which where i am taking the data to be transmitted.
BL_CONST C_UINT16 Kuc_PM_SecondBSL[64] ={0x1111,0x2222,0x3333,0x4444,0x5555,0x6666,0x7777,0x8888,0x9999,0xAAAA,0xBBBB,
0xCCCC,0xDDDD,0xEEEE,0xFFFF,0x1010,0x1111,0x1212,0x1313,0x1414,0x1515,0x1616,
0x1717,0x1818,0x1919,0x1A1A,0x1B1B,0x1C1C,0x1D1D,0x1E1E,0x1F1F,0x2020,0xE6,0x03,
0x03,0x00,0xE6,0x01,0x03,0x00,0xE6,0xF5,0xE0,0x00,0xE6,0xF4,0x58,0x69,0xB8,0x54,
0xE6,0x01,0x81,0x00,0xE6,0xF4,0x48,0x40,0xE6,0xF7,0x00,0x60,0xB8,0x74};
What i am expecting is the same 64 word needs to be received (using General SPI/SPI with DMA) in my Receive Buffer at the location 0x8012D48
While tranferring using General SPI same 64 word are received properly in my Receive Buffer at the location 0x8012D48
But while transferring with DMA i am receiving like this.. at location 0x8012D48 i am receiving 0x0074 instead of 0x1111. 0x0074 is the last word in my array "Kuc_PM_SecondBSL[64]", but it was received in the first location.
Here i have added my code for your reference
1.Code for SPI initialization
FUNC(void, SPI_GLOBAL_CODE) SPI_Init(void)
{
int i;
/*-------------------------------------------------------------------------
Initialize the MibSPI1
-------------------------------------------------------------------------*/
spiREG->SPIGCR0 = 1; /*SPI is out of the reset state*/
/* Pull control Enable */
spiREG->SPIPC7 = 0;
/* Pullup enable */
spiREG->SPIPC8 = 0xFFFFFFFF;
/* SPI Pin functionality selection */
spiREG->SPIPC0 = 0xFFFFFFFF;
/* Select the Clock source & enable master mode */
spiREG->SPIGCR1 =(1U<<16) /* Loop back enable */
|(1U<<1) /* Clock is internally-generated */
|(1); /* Master Mode Operation, SPISOMI pins are inputs, SPISIMO pins are outputs */
/* Select the SPI Data Format */
spiREG->SPIFMT0 =(1U<<29) /* Wdelay = 3F */
|(1U<<28)
|(1U<<27)
|(1U<<26)
|(1U<<25)
|(1U<<24)
|(0U<<22) /* No Parity Generation */
|(0U<<21) /* SPI doesnot wait for the ENA signal from Slave */
|(0U<<20) /* MSB is shifted out first */
|(0U<<19) /* Normal Full duplex transfer */
|(1U<<18) /* CS to transmission delay & transmission to CS delay disabled */
|(0U<<17) /* Polarity = 0 */
|(0U<<16) /* Phase = 0 */
|(0U<<15) /* Prescale to determine bit transfer rate */
|(0U<<14) /* Prescale to determine bit transfer rate */
|(0U<<13) /* Prescale to determine bit transfer rate */
|(0U<<12) /* Prescale to determine bit transfer rate */
|(1U<<11) /* 10Mbps bit transfer rate */
|(0U<<10) /* Prescale to determine bit transfer rate */
|(0U<<9) /* Prescale to determine bit transfer rate */
|(1U<<8) /* Prescale to determine bit transfer rate */
|(1U<<4) /* Char length MSB */
|(0U<<3)
|(0U<<2) /* Char length = 16 */
|(0U<<1)
|(0); /* Char length LSB */
/* Configure the SPI Delay */
spiREG->SPIDELAY = 0;
/*Selecting the Data Format*/
spiREG->SPIDAT1 =(1U<<26) /*Enable WDEL*/
|(0U<<25) /* Data Word format 0 Selected*/
|(0U<<24);
/*******************************
DMA Configuration
*******************************/
/*reset dma*/
dmaREG->GCTRL = 0x00000001;
/* enable dma */
dmaREG->GCTRL |= 0x00010000;
/* stop at suspend */
dmaREG->GCTRL |= 0x00000300;
}
2. Function for SPI transfer using Gen SPI/ DMA SPI
void SPI_Transmit( C_UINT16 *Lpp_Tx_Data,
C_UINT16 *Lpp_Rx_Data,
C_UINT16 Lus_Data_Len,C_UINT8 TX_RX_GEN_SPI_OR_DMA_SPI)
{
C_UINT16 Lucloop ;
C_UINT16 i;
if(TX_RX_GEN_SPI_OR_DMA_SPI == GEN_SPI)
{
spiREG->SPIGCR1 |= (1U<<24); /* Activates SPI (SPIEN =1) */
for(Lucloop=ZERO;Lucloop<Lus_Data_Len;Lucloop++)
{
/* Transmit Data */
while(((spiREG->SPIBUF)&0x20000000) == 0x20000000)
{
;
}
spiREG->SPIDAT0 = *Lpp_Tx_Data;
/* Read Rx buffer */
while(((spiREG->SPIBUF)&0x80000000) == 0x80000000)
{
;
}
*Lpp_Rx_Data = (C_UINT16)spiREG->SPIBUF;
/* Increment buffers */
Lpp_Tx_Data++;
Lpp_Rx_Data++;
}
spiREG->SPIGCR1 |= (0U<<24); /* Deactivates SPI (SPIEN =0) */
}
else if(TX_RX_GEN_SPI_OR_DMA_SPI == DMA_SPI)
{
/****************************************
Initialising the data to be send
****************************************/
GusRxBuffer[0]=0;
for(i=1;i<65;i++)
{
GusRxBuffer[i] = 0;
}
/* Assign DMA request 1 to Chan 1*/
dmaREG->DREQASI[0] |=(1U <<16U);
/* Assign DMA request 0 to Chan 0*/
dmaREG->DREQASI[0] |=(0U <<24U);
/****************************************
TX Configuration
****************************************/
/*Source Address*/
dmaRAMREG->PCP[1].ISADDR =(C_UINT32)Lpp_Tx_Data;
/*Destinaton Address*/
dmaRAMREG->PCP[1].IDADDR =(C_UINT32)0xFFF7F43E;//&spiREG->SPIDAT1;
/*Initial frame transfer count & Initial element transfer count*/
dmaRAMREG->PCP[1].ITCOUNT = (C_UINT32)(((Lus_Data_Len)<< 16U) |1);
/*Channel Control Register*/
dmaRAMREG->PCP[1].CHCTRL = (0<<15)
| (1 << 14) /*Read element size is WORD*/
| (1 << 12) /*Write element size is WORD*/
| (0 << 8) /*A hardware request triggers one frame transfer*/
| (1 << 3) /*Read address Post-increment*/
| (0 << 1) /*Write address fixed*/
| (1); /*Auto-initiation mode is enabled*/
/*Destination address element index and Source address element index*/
dmaRAMREG->PCP[1].EIOFF =0;
/*Destination address frame index and Source address frame index*/
dmaRAMREG->PCP[1].FIOFF =0;
/*Assign PortB for channel 1 */
dmaREG->PAR[0] = (0x04 << 24U);
/*Enable Hardware triggering for channel 1*/
dmaREG->HWCHENAS = (1 << 1);
/****************************************
RX Configuration
****************************************/
/*Source Address*/
dmaRAMREG->PCP[0].ISADDR =(C_UINT32)0xFFF7F442;//&spiREG->SPIBUF;
/*Destinaton Address*/
dmaRAMREG->PCP[0].IDADDR =(C_UINT32)Lpp_Rx_Data;
/*Initial frame transfer count & Initial element transfer count*/
dmaRAMREG->PCP[0].ITCOUNT = (C_UINT32)(((Lus_Data_Len)<< 16U) |1);
/*Channel Control Register*/
dmaRAMREG->PCP[0].CHCTRL = (0<<15)
| (1 << 14) /*Read element size is WORD*/
| (1 << 12) /*Write element size is WORD*/
| (0 << 8) /*A hardware request triggers one frame transfer*/
| (0 << 3) /*Read address fixed*/
| (1 << 1) /*Write Post-increment*/
| (1); /*Auto-initiation mode is enabled*/
/*Destination address element index and Source address element index*/
dmaRAMREG->PCP[0].EIOFF =0;
/*Destination address frame index and Source address frame index*/
dmaRAMREG->PCP[0].FIOFF =0;
/*Assign PortB for channel 0 */
dmaREG->PAR[0] |= (0x04 << 28U);
/*Enable Hardware triggering for channel 0*/
dmaREG->HWCHENAS |= 1;
/*Selecting the Data Format*/
spiREG->SPIDAT1 &= (0xFCFFFFFF); /* Data Word format 0 Selected*/
/*For testing DMA request enable*/
spiREG->SPIINT0 |= (1 << 16);
/* Activates SPI (SPIEN =1) */
spiREG->SPIGCR1 |= (1U<<24);
/* Start Data Transfer */
while(dmaREG->BTCFLAG != 3);
/*Clearing the Interrupt flags*/
dmaREG->BTCFLAG = 3;
/*Disable Hardware triggering for channel 0,1*/
dmaREG->HWCHENAR = (1 << 1)
| 1 ;
}
else
{
/*do nothing*/
}
}
3. My function call will be like this
GppSCI_Command_Buf =(C_UINT16 *) &Kuc_PM_SecondBSL[0];
SPI_Transmit( GppSCI_Command_Buf,GusRxBuffer,64,GEN_SPI);
SPI_Transmit( GppSCI_Command_Buf,GusRxBuffer,64,DMA_SPI);
Please guide me to solve this problem of data reception using DMA.
Thanks & Regards,
Kamala VIgnesh.
