Hi!, we are using TMS570LS3137PGE and HALCOGEN 03.05.02, CCSv5.4.0.00091 and XDS100v2.
We are initializing spi1 in compatibility mode (code below) but the problem is that FMTx registers stays equal 0 (never get set). Using JTAG we can force the registers, save the values, and run as expected.
We double checked with step by step debugging, and on more than one chip. Also, other registers from SPI get set, only the FMTx don't work.
Do you have any clues or ideas?
Thanks,
Santiago
spi1Init(void)
{
/** @b initialize @b SPI1 */
/** bring SPI out of reset */
spiREG1->GCR0 = 1U;
/** SPI1 master mode and clock configuration */
spiREG1->GCR1 = (spiREG1->GCR1 & 0xFFFFFFFCU) | ((1U << 1U) /* CLOKMOD */
| 1U); /* MASTER */
/** SPI1 enable pin configuration */
spiREG1->INT0 = (spiREG1->INT0 & 0xFEFFFFFFU)| (0U << 24U); /* ENABLE HIGHZ */
/** - Delays */
spiREG1->DELAY = (0U << 24U) /* C2TDELAY */
| (1U << 16U) /* T2CDELAY */
| (0U << 8U) /* T2EDELAY */
| 0U; /* C2EDELAY */
/** - Data Format 0 */
spiREG1->FMT0 = (3U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (30U << 8U) /* baudrate prescale */
| 8U; /* data word length */
/** - Data Format 1 */
spiREG1->FMT1 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (12U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - Data Format 2 */
spiREG1->FMT2 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (12U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - Data Format 3 */
spiREG1->FMT3 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (12U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - set interrupt levels */
spiREG1->LVL = (0U << 9U) /* TXINT */
| (0U << 8U) /* RXINT */
| (0U << 6U) /* OVRNINT */
| (0U << 4U) /* BITERR */
| (0U << 3U) /* DESYNC */
| (0U << 2U) /* PARERR */
| (0U << 1U) /* TIMEOUT */
| (0U); /* DLENERR */
/** - clear any pending interrupts */
spiREG1->FLG |= 0xFFFFU;
/** - enable interrupts */
spiREG1->INT0 = (spiREG1->INT0 & 0xFFFF0000U)
| (1U << 9U) /* TXINT */
| (1U << 8U) /* RXINT */
| (0U << 6U) /* OVRNINT */
| (0U << 4U) /* BITERR */
| (0U << 3U) /* DESYNC */
| (0U << 2U) /* PARERR */
| (0U << 1U) /* TIMEOUT */
| (0U); /* DLENERR */
/** @b initialize @b SPI1 @b Port */
/** - SPI1 Port output values */
spiREG1->PCDOUT = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (0U << 8U) /* ENA */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/** - SPI1 Port direction */
spiREG1->PCDIR = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (0U << 8U) /* ENA */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/** - SPI1 Port open drain enable */
spiREG1->PCPDR = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 8U) /* ENA */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/** - SPI1 Port pullup / pulldown selection */
spiREG1->PCPSL = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 8U) /* ENA */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (1U << 11U); /* SOMI */
/** - SPI1 Port pullup / pulldown enable*/
spiREG1->PCDIS = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 8U) /* ENA */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/* SPI1 set all pins to functional */
spiREG1->PCFUN = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (0U << 8U) /* ENA */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (1U << 11U); /* SOMI */
/** - Finally start SPI1 */
spiREG1->GCR1 = (spiREG1->GCR1 & 0xFEFFFFFFU) | (1U << 24U);
}
