Does RECEIVE Interrupt also occurs for DATA Frame for which FRAME Error Occurred in SCILIN Module with SCI Mode?

Pashan,

If both Rx and FE interrupt are enable, that you will have 2 request.
In general, it is recommended to map the error interrupt with a higher priority. In this case your application will service the error handler first.
Within the error handler you will have to take care of clearing the error flag has well as the receive flag so you don't execute the receive handler on this bad data.

Hello Jean-Marc,

In the FE Interrupt [INT0 -- Higher Priority],
I read the SCIRD Register as well as CLEAR FLR Register for FE Bit by wrting 1.
So it will clear the RDY Bit I assume and hence no RX Ineterrupt [INT1 -- Lower Priority] will not occur.
But INTREQ Bit of VIM will not be cleared.
Hence, I am getting SCI RX [INT1] Interrupt for the case where FE Interrupt [INT0] occurred.
Is that correct or something I am missing within FE Interrupt handler?

Thank you.
Regards
Pashan

Pashan,

I did a quick test, and here is the result.

If both FE and RX are interrupt enable in the SCI module as respectively High and Low request, and the VIM Mask is set to capture both interrupt than:

In your FE_Error handler you will have to clear both flag (FE and RX from SCI module) as well as the VIM request corresponding to the RX flag. Otherwise, when you exit your FE_ERROR handler you will jump in the RX_HANDLER.

Hello jean-Marc,

Can you please attach your complete PROJECT Source as ZIP so that I can also build here are understand?

It will be of great help.

Also, how did you generate ERROR that also please tell.
Thank you.
Regards
Pashan

Pashan,

At that point, I don't have a real project that I can share, but I can work on that Monday.

To generate framing error, I'm using a window terminal set as 8bits 1 stop.
In the SCI configuration I'm using 7bits 1 stop.
Using this setup I'm able to generate FE error.

Pashan,

Here is my Halcogen and CCS project for testing the SCI Framing error in TMS570LS3137.

I'm using the SCI_USB from the HDK to receive data from PC. The USB port can also be used for debug.
My window terminal is setup as:9600, 8bits, no parity, 1 stop, no flow control.

On the device side, I have the same configuration.

SCI_Low interrupt for SCI_RX
SCI_High interrupt for SCI_FE.

To generate the framing error, I change the data size from 8 to 7 on the device.
The CPU will jump in void linHighLevelInterrupt(void)

Please let me know if this clarify your question.

2402.SCI_Frame_Error.zip

Hello Jean-Marc,

Thank you for the DEMO.

Following is my question :

1> For usual case of clearing VIM INTREQ, we just clear the Peripheral Side Request either by writing specific Register Status or by reading the specific Peripheral Register VECTOR_OFFSET within Peripheral Register Address SPACE.
But for this case of FRAME_ERROR, even though you are writing 0x200 to SCIFLR Register, why do you need to write to VIM INTREQ Register directly?
I am asking this question, because we use external RTOS which manages all the VIM related Programming and hence we don't have any direct access to VIM INTREQ Bit Mapping related to Peripheral Interrupt Channels.
Once you answer this question, I can ask my supplier for the exact solution.

Regards
Pashan