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ECC FLASH testing

Vivek Shetty
Prodigy 220 points
Other Parts Discussed in Thread: TMS570LS20216, NOWECC

Hi,

I am using TMS570LS20216 USB and I am trying to check ECC flash Check.

Steps followed are as follows:

I have Initialised ESM and Enabled an ERROR pin to trace the channel 6 which is the ECC flash Single Bit error

I have used now ECC to generate the ECC for the 'xxx.out' (my software build) with the below command to force a single bit error

nowecc -s1 0x00000020 1 -i xxx.out -f035 -r4 -0 ecc.hex

And the 'ecc.hex' that is obtained is flashed using the nowflash

The xxx.out is flashed later on which has the ECC flash enable but my checkFlashECC function which callsESM stat register doesn't show the error in the flag

 

 

 

  • 0
    TI__Intellectual 1115 points

    Hi Vivek,

    I have referred this question to one of our subject matter experts who will get back to you. 

    Paul B.

  • 0 in reply to Paul Blecher
    Prodigy 220 points

    Hi Paul,

     

    Any updates on the same?

     

    Thanks,

    Vivek

  • 0 in reply to Vivek Shetty
    TI__Intellectual 1115 points

    Vivek,

    Unfortunately I have not been able to get any ideas on this so far.  Can you please paste the portion of your code which is causing the issue?

    Paul B

  • 0 in reply to Paul Blecher
    Prodigy 220 points

    Hi Paul,

    This ih the code I have for FLASH,

    And looks like it is going the prefetch ISR

    Can you please guide me.

    ; Enable ECC Check for FLASH

    .global _ENABLE_ECC_FLASH_

    .asmfunc

    _ENABLE_ECC_FLASH_:

    MRC p15,#0,r1,c9,c12,#0

    ; Read PMNC register in privileged mode

    ORR r1, r1, #0x00000010

    ; Bit4 enable export of the events to the event bus (send ECC error to the flash wrapper)

    MCR p15,#0,r1,c9,c12,#0

    ; Write PMNC register in privileged mode

    MRC p15, #0,r1,c1,c0,#1

    ; Read Auxiliary control register

    ORR r1, r1, #0x02000000

    ; Bit25 is ATCM ECC check enable

    MCR p15, #0, r1, c1, c0, #1

    ; Write Auxiliary control register

    MRC p15, #0,r1,c1,c0,#1

    ; Read Auxiliary control register

    ORR r1, r1, #0x00000001

    ; Bit0 is ATCM external error into CPU enable

    MCR p15, #0, r1, c1, c0, #1

    ; Write Auxiliary control register

    MOV PC, lr

    　

    .endasmfunc

    Thanks,

    Vivek

  • 0 in reply to Vivek Shetty
    TI__Intellectual 1115 points

    Vivek,

    At which point in the code is it going into prefetch abort? Is it as soon as you enable ECC?

    Paul B 

  • 0 in reply to Vivek Shetty
    TI__Mastermind 22715 points

    Vivek,

    I would like to suggest following for testing Flash  ECC error detection/correction.

    (1) Create the .out file and ECC files as normal. In your test code, you should enable ECC. You also need to set up the Flash wrapper registers to enable an interrupt or a trigger to ESM for single bit error. double bit error will trigger an abort (data abort for data loading and prefetch abort for instruction fetching). You can also disable ECC correction to trigger an abort on single bit error.

    (2) Going through the disasembly file and .map file to find locations (address) where you want to introduce single bit or dobut bit error. You need to make sure that CPU will run to this address.

    (3) Load the .out file of your test code into the simulator and introduce to error in the CCS memory window. Then you can save the memory content back as an .out file. In CCS3.3, there is a bug that the endianess of the .out file is switched. That is, if you load a big endian .out, the .out you save back is in little endian. You will need to load the saved file back and save again to get the saved file in big enadian.

    (4) Programmed the modified .out and the original ECC files.

    I am attching a assembly code to show how to set up abort for single bit error. In the abort routine, you can check CP15 registers to find the cause of the abort.

    4846.boot_flash_ecc_r4_EABI.asm

    3531.coprocessor_EABI.asm

    3603.dabt_pabt_test1_EABI.c

    Thansk and regards,

    Zhaohong

     

  • 0 in reply to Paul Blecher
    Prodigy 220 points

    Yes Paul,

    It enters to Prefetch abort when I include the call to _ENABLE_ECC_FLASH_ function.

     

    Thanks,

    Vivek

  • 0 in reply to Zhaohong Zhang
    Prodigy 220 points

    Hi Zhaohong ,

    I'll check this and get back to you.

     

    Thanks,

    Vivek

  • 0 in reply to Vivek Shetty
    Prodigy 220 points

    Hi Zhaohong,

    I am unable to run my code as it is now getting to the prefetch ISR , when I enable  call the function _ENABLE_ECC_FLASH_

    which has the below piece of code.

    .global  _ENABLE_ECC_FLASH_
     .asmfunc
       
    _ENABLE_ECC_FLASH_:

     MRC p15, #0, r1, c1, c0, #1 
     ORR r1, r1, #0x1 <<25
     DMB
     MCR p15, #0, r1, c1, c0, #1
     ISB
       
    .endasmfunc

     And I have enabled  EDACMODE bits in the FEDACCTRL1 i.e.

    flashWREG->FEDACCTRL1_EDACMODE = 0x0AU, Where flashWREG is the pointer to address 0xFFF87000U

    Dissassembly points at the below memory address          

     

                $../source/sys_intvecs.asm:34:63$:
        0x00000000:   BAD0BAD0 BLT             0xFF42EB48
        0x00000004:   BAD0BAD0 BLT             0xFF42EB4C
        0x00000008:   BAD0BAD0 BLT             0xFF42EB50
    >>0x0000000C:   EAFFFFDE B               Sys_ClkTest
        0x00000010:   BAD0BAD0 BLT             0xFF42EB58
       0x00000014:   EAFFFFFF B               0x18
       0x00000018:   BAD0BAD0 BLT             0xFF42EB60
       0x0000001C:   BAD0BAD0 BLT  

     

    Thanks,

    Vivek

  • 0 in reply to Vivek Shetty
    TI__Mastermind 22715 points

    Vivek,

    There must be something wrong with your Flash programming. Did you programmed ECC? After connecting to CCS, do a system reset. PC should stay at address 0x0. Take a look at CCS memory window to see if the content makes sense when ECC is not enabled.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Prodigy 220 points

    Hi Zhaohong,

    Apologies for the delayed response.

    The PC starts at 0x0 location but as I debug through the _ENABLE_ECC_FLASH_ function it gets into the ABORT prefetch ISR.

    I have initially flashed the ECC into the MicroController using the nowFlash and  checked whether the ECC values are stored from the memory address '0x00400000' by Launching the TI debugger and connecting the target; it seems fine

    Then using the Code Composer IDE I have tried to load the program with Erase option set to neccessary sectors only to debug the ECC functionality

    But when I view the values in the memory window that is at the address 0x00400000 the value are set as all 'F's.(looks like the ECC values are getting overwritten with all 'F's)

    Also as mentioned when I parse through the ''_ENABLE_ECC_FLASH_' it enters to ABORT prefetch ISR.

    This function has the assembly code as mentioned in the page 274 of spnu489c. Am I missing something ?

    Please guide me.

    Thanks,

    Vivek