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TM4C123 ADC acquisition timing

SourceTwo
Expert 2355 points

Hello TI,

I need to sample analog signal(s) at a precise time relative to a PWM output.  For this I am using a PWM-trigger (from a spare PWM generator) set to fire "early" in order to start the ADC, acquire a sample, and have the sampling window close at the optimal time.  My questions center around this objective.

From the data sheet, there are two specifications of interest:

1. T_lt - Latency from trigger to start of conversion.

This nominally 2 ADC clocks.  Are minimum and maximum values available (assuming the ADC is initially idle)?

2. T_c - ADC sample time.

Does the sample window close at about 6 ADC clocks (~2 clocks + 250nS)  from the trigger?

Can I expect the succeeding samples in a sequence are acquired 16 ADC clocks apart?

I appreciate any assistance you can offer!  Also, please accept my vote for a data sheet enhancement showing the ADC timing (ala SSI, I2C etc...).

 

Regards,

Dave

  • 0
    Expert 2355 points

    Hello TI,

    Can one of you have a look at this please?  Thank you!

    Regards,

    Dave

  • 0 in reply to SourceTwo
    TI__Genius 10040 points

    My apologies for the delayed response.  I've forwarded your questions to the design engineers.  I am still waiting on additional responses.  I hope to have them by the end of the day today.  I will try to follow up by COB today with what information I am able to track down.

    --Bobby

  • 0 in reply to Bobby Bradford
    TI__Genius 10040 points

    I am still waiting on additional information, but here is what I have at this time.

    Regarding inquiry 1, we do not at this time spec min/max values.  However, my understanding of how the PWM triggers for ADC work is that there is a clock-domain crossing that transfers the PWM triger from the PWM/System Clock domain to the ADC clock domain (16 MHz).  This will introduce from just over 1 clock cycle to just over 2 clock cycles, depending upon the arrival of the trigger to the ADC clock domain relative to the required setup time.  One additional piece of information that I am waiting for is if there are additional clocking delays that may be in the trigger path, or if the signal routing would contribute significant delays relative to the ADC clock period.

    Regarding your second inquiry, the answer to the first question is yes, it will be 4 ADC clocks (250ns) + Latency (nominal 2 ADC clocks, with exceptions as noted above).  The answer to the second question is yes, subsequent ADC samples are 16 ADC clocks apart.

    --Bobby

  • 0 in reply to Bobby Bradford
    Expert 2355 points

    Excellent - thank you Bobby!

    Sincerely,

    Dave