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Setting for Direct Data Mode in DMM

Other Parts Discussed in Thread: HALCOGEN

Hi.  I'm trying to use DMM in direct data mode to get some data from an external device.  8 Data, clock, and sync pins are being used.  I have used Halcogen 03.06.00 to generate startup code necessary for the Hercules to get up and running.  In Halcogen, I've enabled only the GIO and DMM drivers.  I had to add a little bit of my code inside the function dmmInit generated by the Halcogen.  I've pasted my code below.  You can see that in the function main, I called the function dmmInit, initialized the data buffer to some known number, and then kept polling and printing the first byte of the buffer to see if the content is different.  Somehow it's not working, the content of the first byte of the buffer to stuck to the initialized value even though there are data are coming into the pins.  I'd like to make sure the register settings I have for the DMM is correct before I proceed to debug to the external device.  Could anyone please help?

#pragma DATA_ALIGN(gucDmmBuffer, 256);
unsigned char gucDmmBuffer[256];

void dmmInit(void)
{
    /* USER CODE BEGIN (2) */
    /* USER CODE END */

    /** @b intalise @b DMM */

    /** @b initialize @b DMM @b Port */
    dmmREG->PC3 =  0U                  /* DMM SYNC */
                                    | (0U << 1U)     /* DMM CLK */
                                    | (0U << 2U)     /* DATA[0] */
                                    | (0U << 3U)     /* DATA[1] */
                                    | (0U << 4U)     /* DATA[2] */
                                    | (0U << 5U)     /* DATA[3] */
                                    | (0U << 6U)     /* DATA[4] */
                                    | (0U << 7U)     /* DATA[5] */
                                    | (0U << 8U)     /* DATA[6] */
                                    | (0U << 9U)     /* DATA[7] */
                                    | (0U << 10U)   /* DATA[8] */
                                    | (0U << 11U)   /* DATA[9] */
                                    | (0U << 12U)   /* DATA[10] */
                                    | (0U << 13U)   /* DATA[11] */
                                    | (0U << 14U)   /* DATA[12] */
                                    | (0U << 15U)   /* DATA[13] */
                                    | (0U << 16U)   /* DATA[14] */
                                    | (0U << 17U)   /* DATA[15] */
                                    | (0U << 18U);  /* DMM ENA */

    /** - DMM Port direction */
    dmmREG->PC1 =  0U                  /* DMM SYNC */
                                    | (0U << 1U)      /* DMM CLK */
                                    | (0U << 2U)      /* DATA[0] */
                                    | (0U << 3U)      /* DATA[1] */
                                    | (0U << 4U)      /* DATA[2] */
                                    | (0U << 5U)      /* DATA[3] */
                                    | (0U << 6U)      /* DATA[4] */
                                    | (0U << 7U)      /* DATA[5] */
                                    | (0U << 8U)      /* DATA[6] */
                                    | (0U << 9U)      /* DATA[7] */
                                    | (0U << 10U)    /* DATA[8] */
                                    | (0U << 11U)    /* DATA[9] */
                                    | (0U << 12U)    /* DATA[10] */
                                    | (0U << 13U)    /* DATA[11] */
                                    | (0U << 14U)    /* DATA[12] */
                                    | (0U << 15U)    /* DATA[13] */
                                    | (0U << 16U)    /* DATA[14] */
                                    | (0U << 17U)    /* DATA[15] */
                                    | (0U << 18U);   /* DMM ENA */

    /** - DMM Port open drain enable */
    dmmREG->PC6 =  0U             /* DMM SYNC */
                | (0U << 1U)      /* DMM CLK */
                | (0U << 2U)      /* DATA[0] */
                | (0U << 3U)      /* DATA[1] */
                | (0U << 4U)      /* DATA[2] */
                | (0U << 5U)      /* DATA[3] */
                | (0U << 6U)      /* DATA[4] */
                | (0U << 7U)      /* DATA[5] */
                | (0U << 8U)      /* DATA[6] */
                | (0U << 9U)      /* DATA[7] */
                | (0U << 10U)    /* DATA[8] */
                | (0U << 11U)    /* DATA[9] */
                | (0U << 12U)    /* DATA[10] */
                | (0U << 13U)    /* DATA[11] */
                | (0U << 14U)    /* DATA[12] */
                | (0U << 15U)    /* DATA[13] */
                | (0U << 16U)    /* DATA[14] */
                | (0U << 17U)    /* DATA[15] */
                | (0U << 18U);   /* DMM ENA */


    /** - DMM Port pullup / pulldown selection */
    dmmREG->PC8 =  1U             /* DMM SYNC */
                | (1U << 1U)      /* DMM CLK */
                | (1U << 2U)      /* DATA[0] */
                | (1U << 3U)      /* DATA[1] */
                | (1U << 4U)      /* DATA[2] */
                | (1U << 5U)      /* DATA[3] */
                | (1U << 6U)      /* DATA[4] */
                | (1U << 7U)      /* DATA[5] */
                | (1U << 8U)      /* DATA[6] */
                | (1U << 9U)      /* DATA[7] */
                | (1U << 10U)    /* DATA[8] */
                | (1U << 11U)    /* DATA[9] */
                | (1U << 12U)    /* DATA[10] */
                | (1U << 13U)    /* DATA[11] */
                | (1U << 14U)    /* DATA[12] */
                | (1U << 15U)    /* DATA[13] */
                | (1U << 16U)    /* DATA[14] */
                | (1U << 17U)    /* DATA[15] */
                | (1U << 18U);   /* DMM ENA */


    /** - DMM Port pullup / pulldown enable*/
    dmmREG->PC7 =  1U          /* DMM SYNC */
                | (1U << 1U)   /* DMM CLK */
                | (1U << 2U)   /* DATA[0] */
                | (1U << 3U)   /* DATA[1] */
                | (1U << 4U)   /* DATA[2] */
                | (1U << 5U)   /* DATA[3] */
                | (1U << 6U)   /* DATA[4] */
                | (1U << 7U)   /* DATA[5] */
                | (1U << 8U)   /* DATA[6] */
                | (1U << 9U)   /* DATA[7] */
                | (1U << 10U) /* DATA[8] */
                | (1U << 11U) /* DATA[9] */
                | (1U << 12U) /* DATA[10] */
                | (1U << 13U) /* DATA[11] */
                | (1U << 14U) /* DATA[12] */
                | (1U << 15U) /* DATA[13] */
                | (1U << 16U) /* DATA[14] */
                | (1U << 17U) /* DATA[15] */
                | (1U << 18U);/* DMM ENA */

    /* DMM set all pins to functional */
    dmmREG->PC0 =  1U           /* DMM SYNC */
                | (1U << 1U)    /* DMM CLK */
                | (1U << 2U)    /* DATA[0] */
                | (1U << 3U)    /* DATA[1] */
                | (1U << 4U)    /* DATA[2] */
                | (1U << 5U)    /* DATA[3] */
                | (1U << 6U)    /* DATA[4] */
                | (1U << 7U)    /* DATA[5] */
                | (1U << 8U)    /* DATA[6] */
                | (1U << 9U)    /* DATA[7] */
                | (0U << 10U)  /* DATA[8] */  
                | (0U << 11U)  /* DATA[9] */  
                | (0U << 12U)  /* DATA[10] */  
                | (0U << 13U)  /* DATA[11] */  
                | (0U << 14U)  /* DATA[12] */  
                | (0U << 15U)  /* DATA[13] */  
                | (0U << 16U)  /* DATA[14] */  
                | (0U << 17U)  /* DATA[15] */  
                | (1U << 18U); /* DMM ENA */  

/* USER CODE BEGIN (3) */
    /* set the Direct Data Mode destionation register */
    dmmREG->DDMDEST = (uint32)gucDmmBuffer;
    /* set the Direct Data Mode blocksize to 256 bytes */
    dmmREG->DDMBL = 0x4;
    /* start the DMM module */
    dmmREG->GLBCTRL = (1U << 8U)  /* Direct Data Mode */
                    | (1U << 10U)
                    | (0U << 9U)  /* DDM Width to 8 bits */
                    | (1U << 3U)
                    | (1U << 1U);  /* turn on the DDM mode */
/* USER CODE END */
}

void main(void)
{
/* USER CODE BEGIN (3) */
    int i;

    dmmInit();


    for(i = 0; i < 256; i++)
        gucDmmBuffer[i] = 0xA5;
    while(1)
    {
        printf("DMM Data Ptr location: %d\n", gucDmmBuffer[0]);
    }
/* USER CODE END */
}

  • Hello Max,

    I have forwarded your question to one of our DMM experts. They will be getting back with you soon.

  • Hi Max,

    Which MCU are you using?

    Does the sending device wait for the DMMnENA signal to go low before it starts driving the DMM port?

    Regards, Sunil

  • Hello, Sunil.  I'm using RM48, L952ZWTT.  I'll have to check with the person that is doing the transmission from a fpga.  The signal lines for the DMM pins are all buried and I have no way to probe.  I'll get back with you on that.

    Meanwhile, could you check my register configuration to see if it is comprehensive and correct?  I'm not trying to use an interrupt for the DMM interface.

    One thing I left out in the code mentioned above is the potential pin mux setting generated by the Halcogen.  I'm supposed to enable the DMM in the pin mux section of the Halcogen, right?

  • Hello Max,

    Sorry for the delay. The DMM functions that are multiplexed are all inputs, and these inputs are all broadcast to each function. So it is not critical to enable multiplexing control for selecting the DMM functions. It is preferred, however, so that no other multiplexed function begins to drive these terminals as outputs.

    I see that you have configured DMMnENA as a functional signal. In that case, the external circuit does need to wait for this signal to be active before it starts sending the data to the DMM port. Can you confirm that this is the case?

    Regards, Sunil

  • thanks Sunil.  A person here helped me out with the DMM communication.  Everything is now working as expected.

    Best regards,

    Max