As referred in this two posts:
http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/239783/842263.aspx#842263
http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/286814/1001004.aspx#1001004
"the ADC does not automatically reconfigure the "G1 BLOCKS" field of the Group1 DMA control register, so that the application must rewrite the number of results you need to accumulate before generating the next DMA request."
so the DMA cannot be used to implement a double buffering larger than the small limit of ADC RAM. So:
"there is no advantage in using the DMA to read samples compared to an ADC-ISR at the end of a group of samles."
AFAIK this problem makes it impossible to use data coming from a continuous ADC at high speed (1M sample or more) because the CPU cannot follow that speed in a ISR called at 8KHz or more.
I'm I right or there are other solutions to implement a larger double buffering (or a bug workaround)?
If an alternative solution exists can TI share the complete code to implement is? (being a bug I think it should).
