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help in understanding how can i test the clock

Chitra Sapre
Intellectual 320 points

Other Parts Discussed in Thread: HALCOGEN

Hi,

Need help in understanding how can i test the clock. If you have some example that would do. Also i tried to take it through DCAN and SCI but it doesnt give output.

i want to test the clock at 80, 100, 120 MHz.

Please reply.

Regards

Chitra

  • 0
    TI__Guru 59540 points

    Hello Chitra,

    I have split this from the original thread since it is a change in topic.

    Can you provide more details on how you want to test the clock? i.e., do you simply want to bring the clock out of the device and check the frequency with an external oscilloscope for verfication of the clocks or is there some external device that will check it in your application?

    If you are simply trying to bring the clock out, you can configure the ECLK pin through the ECP control registers in the system module to output a clock derived from HCLK but, since it is divided down you would have to multiply any resultant frequency to verify the operating clock. If this is simply a bench test you could configure the CLKTESST functionality to bring the PLL output directly to a pin. The requirements for these are described in the device TRM, spnu489c.pdf, which is available on TI.com.

  • 0 in reply to Chuck Davenport
    Intellectual 320 points

    Hi

    thank you for splitting the thread. I am not sure about the reasonbut I am unable to crate a new post. I dont see that button on my webpge.

    Yes, you are right i simply want to bring the clock out of the devie and see that on scope. can you tell me how can i configure. I tired to set test registe and PLLCTL3 i have already configured but still i am unable to get the clock out. also at what pin it will come out? if you have some example it would be good for understanding.

    Thank you

    Chitra

  • 0 in reply to Chitra Sapre
    TI__Guru 59540 points

    Hello Chitra,

    See the attached pdf of a page from spnu499B Technical Reference Manual. This section discusses the use of the CLKTEST register for bringing out a clock source directly to the ECLK pin and the CLKSRC valid status to N2HET[12] pin.

    7651.spnu499b p121.pdf

    PLLCTRL3 configures PLL2 so if this is the clock source you are wanting to look at you would configure the SEL_ECP_PIN and SEL_GIO_PIN fields to 0110b. Then you would enable the clock test mode by writing 0x5 to the CLK_TEST_EN field of this register. 

    Note that the register diagram appears to be missing the SEL_GIO_PIN. This field is located at bits8-11 of the same register.  I am going to submit a ticker to have the register diagram corrected.

  • 0 in reply to Chuck Davenport
    Intellectual 320 points

    hi

    Thank you for response.

    do you have code snippet for "CLKSRC" and "CLKTEST" as i have tried taht option but it did not give me any result. that is why i started using PLLCTRL3. basically i want to configure clock in 2 to 3 different speed and test it.

    Please suggest option and provide example. I am using reference manual but somehow for clock it is not working out as explained.

    Regards,

    Chitra

  • 0 in reply to Chitra Sapre
    TI__Guru 59540 points

    Hello Chitra,

    Can you tell me which device you are using and which kit if you are using a kit? This will help me make a suitable project demonstrating this feature for the specific device/kit you are using.

    Also, is your preference to bring out PLL1, PLL2 or someother clock signal on the ECLK pin?

  • 0 in reply to Chuck Davenport
    Intellectual 320 points

    Hi

    I am using 20216 development board from TI. I want to bring out sytem clock out and PLL1.

    Can you also tell me how can i enable different peripherals on the same chip?

    Regards

    Chitra

  • 0 in reply to Chitra Sapre
    TI__Guru 59540 points

    Hello Chitra,

    For the CLKTEST function, you may only output one clock at a time. I will generate a project that will do this with one of the two clocks you mention and given that you should be able to enter a different value to the CLKTEST register and select any other clock listed in the documentation for CLKTEST src select. Given Monday is a holiday here in the US, I will try to have the code generated and posted sometime mid next week.

    In regard to enabling multiple peripherals, I would advise you review the TRM architecture section which will describe initialization of the PCR registers as well as the PENA bit within the CLKCNTL register in the system frame.

    Once the PCR registers and PENA values are initialized, there are individual reset bits in each peripheral IP that will need to be brout out of the reset state. These are described in each of the peripheral chapters within the reference manual as well.

    If you use Halcogen, the peripherals will be enabled on a system level via the system startup code generated. In addition, each of the drivers you enable will have an init function that can be called from main that will bring the module out of reset and initialize it as you have configured it in Halcogen.

  • 0 in reply to Chuck Davenport
    TI__Guru 59540 points

    Hello Chitra,

    Attached is a project I created with Halcogen 3.06 and compiled using CCS5.4 for the LS20216 MDK. Unfortunately, I wasn't able to locate any hardware to fully test the example, but this should give you an idea of how to setup and use the CLKTEST feature. Note that I did not set this up to output the PLL since there is a limitation on the ECLK pin that you can only output a maximum of 80MHz. I set it up to output VCLKA1 instead which is derived from the PLL. Feel free to try the direct 160MHz PLL output but you may see issues with the cleanliness of the signal or amplitude issues due to the speed of the output buffer.

  • 0 in reply to Chuck Davenport
    Intellectual 320 points

    hi

    I am unable to get the attachments. Please post the same.

    Regards

    Chitra

  • 0 in reply to Chuck Davenport
    Intellectual 320 points

    hi

    I am using 20216. I am writing a RAM test functionality in which i want to write specific pattern to RAM and read it back. I am unable to compile assembly code for the same. Can you please help me in translatting attached C code to assembly.

    c code file is attached. i am trying to convert same code into assembly.

    Also need definition file for function "uint32 gioGetPort(gioPORT_t *port)"

    Thanks

    Chitra

  • 0 in reply to Chitra Sapre
    TI__Guru 59540 points

    Hello Chitra,

    Please try and compile the C code and use the compile option to enable a list file output. This will give you the ASM code you want. Under the help section of CCS you will find the TI ARM Compiler user's guide which have instructions on how to generate the absolute listings as well as information how to setup the ASM program.

    The definition/header file that has the prototype for the function gioGetPort is gio.h and is in the project I sent you. However, this driver is not included in the project since I did not generate any code for drivers with the project. If you want to generate this code, please download and install Halcogen and select the drivers you want to include in your project.