HalCoGen 3.06 and the VCLK3 Divider Question

Hi,

I wish to set VCLK3 to 80MHZ for use with the EMIF on RM48HDK.  The crystal into PLL1 is 16Mhz, PLL1 is giving 320MHZ and I have set VCLK3 divider to 3 and enabled VCLK3 config button in the GCM page of HalCoGen V3.06.

The code produced in system.c is as follows:

systemREG2->VCLKACON1 = ((1U - 1U ) << 24U) 
                           | (0U << 20U) 
                           | (SYS_VCLK << 16U)
                           | ((1U - 1U ) << 8U)
                           | (0U << 4U) 
                           | SYS_PLL2;

Because I have set the divider to 3, as per spnu503b.pdf, table 2-75 bit field 10-8 the actual ratio bit should be 2 (= divide 3)
Therefore I think there is a bug in the above generated code and it should read:

systemREG2->VCLKACON1 = ((1U - 1U ) << 24U) 
                           | (0U << 20U) 
                           | (SYS_VCLK << 16U)
                           | ((3U - 1U ) << 8U)
                           | (0U << 4U) 
                           | SYS_PLL2;

Can anyone from TI please confirm.

Thanks
Stomp!.