Hellow!!! How can I controle system cycle count in TMS570LS3137 using IAR?
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Hellow!!! How can I controle system cycle count in TMS570LS3137 using IAR?
Debuging TMS570LS1227 program in IAR I use "View->Register->Current CPU Registers" page to controle CYCLECOUNTER register. But I can't find this register debugin TMS570LS3137. How can I resolve this problem?
There is no register within the Hercules MCU called CYCLECOUNTER. Is the CYCLECOUNTER register something within your debug hardware in your IAR setup? Have you asked for support from IAR?
Hello,
It is still not very clear what you are trying to accomplish. Assuming you want to slow down a section of code for debug purposes, you could put a break point at the start of the section of code you are trying to debug. Once the execution halts at the breakpoint, you can change the clock parameters by wither using a function generator to replace OSCIN and reduce OSCIN (the effectiveness of this is dependent on how slow you want to go). A second methodology if HCLK is derived from the PLL output, might be to change the PLL settings (PLLCTL1 and PLLCTL2) in the control register view of the IDE to achieve the speed you want but be aware of the PLL setting limitations in regard to divider and multiplier values.
Note that this does not change the cycles to execute the code but each cycle becomes longer in time. Also, be sure to restore the settings back to the regular clock setup once leaving the code section if you want to run the remainder at speed.
Please let me know if this helps.
Hellow! I need to determine computational time of function. I use such equation: Tfunc = Tvclk * Nfunc, Tfunc - computational time of function; Tvclk - vclk period; Nfunc - number of vclk clocks during execution of function. I use IAR for developing code. So, how can I determine Nfunc?
Please take a look at the PMU (performance monitoring unit) in the Cortex R4 CPU. The PMU is accessed via the coprocessor interface. There are built in event counters and a cycle counter which can be used for application profiling.
Regards,
Karl
I'm sorry, I do not have any experience with the IAR tool. You can reference the PMU documentation from ARM on their website: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363e/index.html
Please reference chapter 6, "Events and Performance Monitor".
Regards,
Karl
Pardon - as I read/review this struggle - present here IAR's capture & report of "Cycle Counter" and similar - perhaps of some value. (this data acquired from an LX4F, Stellaris MCU.
Like the (imaginatively named) poster - my (multiple) reads of LX4F manual - and search through Register Listings - revealed no "easy means" to acquire these counts. (odds high that I missed - even w/a fair search)
Believe the value of such tool is primarily one of "code-block comparison" - as officals have stated - not much can be done to alter cyclic requirements of an instruction.
The cycle counter you show on a Cortex M device works in the same fashion as the cycle counter in the PMU. The main difference is that the feature is memory mapped on the Cortex M and on the coprocessor interface Cortex R and Cortex A. The same functionality is present in all three ARM profiles, although with two different implementations.
The real challenge here is to determine if IAR has chosen to make such data available in their tool for the Cortex R processor. For this point, we need someone familiar with IAR to respond. With the TI debugger the register can be viewed.
Best Regards,
Karl
@ KGreb,
Thanks for that. As we have multiple seats, paid IAR - I will initiate a request and report here re: Cortex R. (we've not yet employed that beast - but it is on our radar)
I past spent 2-3 hours - seriously reviewing M4 manual - and could not discern any MCU Register which echo'ed the contents I've displayed. (combed both IAR's register presentations - and found nothing of use w/in MCU manual) In addition - good hour on the ARM site - and failed in that pursuit as well.
Perhaps you've provided a great clue - "feature is memory mapped w/in Cortex M." Would you be so kind to detail, "where w/in Cortex M memory" I should search? As this data is near "live" - suspect it must be stored in SRAM - but am willing to perform such search and present for the benefits of others, here.
Thanks again...
Hi CB1,
On the Cortex M3 and M4 the cycle counter is part of the DWT module. Look for the CYCCNT register (0xE0001004). Please note the that DWT is an optional module in some versions of Cortex M3 and I believe all versions of Cortex M4. The equivalent feature is always available on the Cortex R4/R5 cores.
Best Regards,
Karl
Hi Karl,
You Sir - very much, "da man!" (Bears (2-0!) fan here)
Just as you indicated - Cycle Counter alive/well @ E000.1004 - w/in our firm's multiple LX4F MCUs.
Note that 0x00180b14 = 1575700 - thus IAR & this register access agree. (memory shown is in 4 byte chunks - little ended) I did have to manually "clear" this location - as it "defaults" to a consistent value - prior to hitting targeted breakpoint. After that clear - results here & via IAR Cycle Counter match.
To keep my promise - I'm searching now for TMS570 care/handling under IAR 6.60 - and will post here my findings.
Thanks again - much appreciated...
@ Karl/interested others,
We find some 20 "TMS570LS" devices listed w/in ver 6.60 IAR. However - the, "Project -> Options list box is only 1/4 (or even less) the size of our "usual" - when operating w/Cortex M3/M4. (clearly we're missing libraries & other needed parts...)
Suspect that I need some link/description of "starting w/TMS570 family" - to far better enable this project box - so that some comment upon IAR's ability w/TMS may be found & shared.
We're not averse to purchasing a representative, "starter kit" - if that will assist in this effort...