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FLEE Bank 7 Read when Error Correction is DISABLED

Pashan None
Genius 5660 points

Hello Support,

In the FLEE Bank 7, within EE_CTRL1 Register I have setup
EE_EDACEN = 0x0A, EE_EDACMODE = 0x05.
That means ERROR DETECTION is enabled and ERROR CORRECTION is disabled.

Under the above mentioned condition when CPU read access from FLEE Bank 7 CELL contents, is it always guranteed CPU will read the exact FLEE Bank 7 CELL contents even when there is ECC Errors present in the 64+8 Bits of DATA+ECC contents for a particular 64-Bit DATA Contents.

Or, under ECC Errors, the DATA+ECC information as read by CPU will not match with the exact Bank 7 CELL contents?

Thank you.
Regards
Pashan

  • 0
    TI__Genius 11645 points

    Hello Pashan,

    Bank-7 access is routed through the AXI interface of CortexR4 and not the TCM.

    In this case the Flash controller will do the Detection/Correction and send only the data to the CPU when Bank-7 is accessed.

    If you disable the error correction, what ever data is present in Bank-7 will be read by the CPU without correction.

    Best Regards,

    Karthik.

    PS: If this answers your question, please click verify answer to close this thread.