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ADC interrupt and overrun

matteo lucarelli
Genius 3265 points
Other Parts Discussed in Thread: HALCOGEN

Hi,

I'm using ADC on TMS570Ls3137HDK.

In the HalCoGen VIM table there are ADC1 and ADC2 Mag interrupts. What they are?

How can I serve the ADC overrun interrupt enabled by GxINTENA bit 1? There's no ADC overrun in the VIM table.

BTW: The overrun flag requires to enable the overrun interrupt to work?

Thank you

  • 0
    TI__Mastermind 49120 points

    Hi Matteo,

    Each ADC module on the LS3137 MCU can generate 4 separate interrupt requests to the VIM.

    Three of these interrupt requests are generated for events related to group conversions. These interrupt conditions are indicated in the respective group's interrupt flag registers: ADEVINTFLG, ADG1INTFLG and ADG2INTFLG. There is also a corresponding group interrupt enable register for each group. That register holds the enable bits for each of the the group interrupt conditions.

    The group interrupt conditions are:

    • End of single conversion sequence (useful for single conversion mode)
    • Completion of number of conversions programmed in the interrupt threshold register
    • Completion of more number of conversions than can be held in the memory allocated for that group
    Suppose you are using the conversion group1. When the ADC generates a group1 interrupt (VIM channel 15 for ADC1 by default), the ISR would then read the interrupt flag register to identify the actual cause for the interrupt based on the three flags for the above conditions.
    The magnitude compare interrupt is independent of the conversion group being used. This interrupt is based on a selected channel number and can generate an interrupt if the conversion on this selected channel is greater than or equal to or less than a reference value. This reference value can be a fixed (programmable) value or can be the conversion result of another channel.
    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Genius 3265 points

    So how can I serve the ADC overrun interrupt enabled by GxINTENA bit 1?

  • 0 in reply to matteo lucarelli
    TI__Mastermind 49120 points

    Here's what the reference manual states:

    19.5.3 Group Memory Overrun Interrupt
    An interrupt can be generated for each group if the number of ADC conversions for that group exceed the
    number of buffers allocated for that conversion group. The application program can choose to read out all
    the conversion results using the CPU or the DMA. Alternatively, the application program can set the
    group’s OVR RAM IGN bit and allow the ADC module to overwrite the group’s results’ memory contents
    with new conversion results.

    If you don't care for the conversion results already accumulated in memory, you can also choose to reset the group's FIFO by writing a new non-zero value to the group's channel selection register, thereby starting a completely new conversion sequence and throwing away all the results that are accumulated in the memory.

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Genius 3265 points

    Is the overrun interrupt intercepted by the same ISR used to intercept the threshold interrupt?

    If I enable the overrun interrupt where can I verify it?

  • 0 in reply to matteo lucarelli
    TI__Mastermind 49120 points

    Matteo,

    Yes, the overrun condition is one of the three causes of the group interrupt. The group interrupt ISR can check the group's INTFLG register to identify the actual cause of the interrupt. If you enable only the overrun interrupt condition, then you can verify that a group interrupt is generated when an overrun condition occurs.

    Regards, Sunil