Hi TI experts,
I am trying to understand the ECC (SECDED) scheme used in TMS50LS31x.
According to SPNA126, during read access, the ECC is re-calculated and
Syndrome = stored_ECC xor re-calculated_ECC#
The note 2 of Tab. 5-1 in SPNU499B states that “Each ECC[x] bit represents the XOR of all the data bits marked with x in the same row”.
I assume it means “Each ECC[x] bit represents the XOR of all the data bits marked with x in the same row, and then XOR the parity bit”.
The interpretation of syndrome byte is given in Tab. 5-3 in SPNU499B.
Just to verify my understanding of the ECC algorithm, I tried the following calculation:
Write 0x0 to flash address 0x0.
First calculate the parity byte, it is 0x0C (according to Tab. 5-3 in SPNU499B).
Then calculate the ECC, it is parity byte xor (all bits marked with x in Tab. 5-3) = 0x0C xor 0x00.
Therefore stored_ECC = 0x0C. (This way I can explain why the ECC for all data in TCRAM after initialization is 0x0C as described in Section 6.4 of SPNU499B).
If the bit 0 at address 0 is corrupted, the data at address 0x0 will be changed to 0x1. During read access, re-calculate ECC:
First calculate the parity byte, it is 0xF3 (according to Tab. 5-3)
Then calculate the ECC, it is parity byte xor (all bits marked with x in Tab. 5-3) = 0xF3 xor 0xE3.
Hence, the re-calculated_ECC = 0x10.
Finally calculate syndrome: syndrome = stored_ECC xor re-calculated_ECC = 0x0C xor 0x10 = 0x1C.
Look up in Tab. 5-3, I get D15 which means data bit 15 is corrupted. But actually bit 0 was corrupted, and I expect the syndrome to be 0xE3 (which maps to D00 -- single bit erro at bit 0).
Now the question: Where did I make the mistake? If the parity bit is not included in the ECC calculation, how to get the ECC code 0x0C as described in section 6.4 of SPNU499B?
One more question: The address bits are not included in the ECC calculation for TCM RAM, will the syndrome table be different from Tab. 5-3 in SPNU499B?
Thank you for the support!
Regards,
Libo
