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Re : Flash Access

Santosh PG
Expert 1590 points

Hi Everyone,

We are using external flash(S29GL512N) which can be accessed through parallel port, we use 2 TIVA 64 pin microcontroller and want to interface to single flash. so is it possible to access single flash using 2 MCU's via parallel ports??

Best Regards,

Santosh.

  • 0
    Guru 117855 points

    Santosh PG said:
    We are using external flash(S29GL512N)

    And - have you noted this (bit familiar) advisory:

    "This product family has been retired and is not recommended for designs. For new and current designs,
    S29GL128P, S29GL256P, and S29GL512P supersede S29GL128N, S29GL256N, and S29GL512N
    respectively. These are the factory-recommended migration paths."

    You are aware that this memory device includes 26 address lines, 16 data lines, and usual suspects: CE, OE & WE - thus exceeding or severely challenging the GPIO of your 64 pin MCU.  (we note 49 GPIO on our earlier LX4F MCU - 4 of those being JTAG)

    Technically you can "bit-bang" GPIO to serve as address, data & control bus.  (as you could launch a Ferrari - on NYC's 5th Ave - against traffic - @ rush hour) 

    Earlier, certain Stellaris (now - effectively abandoned)  had "exernal bus" capability - far more suitable for such external memory purposing.  "Hints" have surfaced that such capability may return - this vendor - this space.

    Two "bus-less" MCUs - coerced into some compliance - do not quite rise to - "best practice" memory cops - imho...

  • 0 in reply to cb1_mobile
    Expert 1590 points

    Hi,

    Thanks for your reply.

    I need to confirm, if we can access the same flash with 2 external MCU's one at a time??

    Best Regards,

    Santosh.

  • 0 in reply to Santosh PG
    Guru 117855 points

    Earlier charted the GPIO requirements: MCU -> Memory.  If your MCU is in the ballpark of our (LX4F - 49GPIO) you will have exhausted nearly every pin. 

    And - you must, "tri-state" each/every MCU pin as it relinguishes memory access.  (likely achieved via open drain outputs or changing all ports from output to input)

    Developing your code - with several of the JTAG pins likely "lost" to memory duty - may prove a challenge.   Have you considered that?

    It is possible to drive a fast/sleek sportscar - during rush hour - on a crowded city street.  But - would you want to?

    And that's quite close to the situation your proposed memory interface presents...

  • 0
    Intellectual 485 points

    Hi,

    of course it can, with good design of hardware and software, it is possible.

    But, as CB1 states, bit banging will do the job at a slow speed. 

    If you want to preserve pins on your uC, you may run the flash in byte mode and if you use external address latches, you may need as little as 3 8-bit ports on each uC. But remember external pull up resistors on at least CE# and you can probably use the uC's internal pull up resistors on other control signals to the flash. 

    You also may read up on semaphores etc. since the software will be responsible for timing and arbitration.

    Good luck