HalCoGen - PLL - Multiplier Correction (MULMOD)

1<<8 means 256.

Section 10.8 provides an example, it explains how to set the FMPLL.

This FMPLL is down modulating (different from the TMS57020216 center modulate ). So, after modulating the center freq is lower than what you expected. Now, if you want to keep the same frequency, you can set MULMOD to keep the center frequency same. For example:

If the frequency is 160MHz, you modulate it to 100KHz, the center frequency becomes 160MHz - 50KHz. Now you need to set MULMOD to increase the frequency back to 160MHz.

Regards,

Haixiao

Ok, thanks.

The user manual says, that "Multiplier Correction" (MULMOD) can be set from 0 to 511,
but I can change the value in HalCoGen (by clicking the small arrows!) only from 7 to 255.

Are the other values (e.g. '0' or '511') not allowed for MULMOD?

Another question. Which value has to be placed for 'f OutpuCLK'?
The value for the baseline frequency ("f baseline", see UM page 373) Output CLK? So StepSize would be constant...

Or is it always the actual frequency of th modulated Output CLK? So, the StepSize will be different each step...

Best regards, Andy

So, your question is whether the Output clock is the modulated clock or the clock without modulation. I dont know the answer. But the difference between them is less than 0.1% (assume a 160MHz clock and 100kHz modulation depth). Any way, I will forward your question to the PLL expert.

If any discrepancy between HalCogen and TRM/Datasheet, you should follow the TRM/Datasheet.

Regards,

Haixiao

You use the output frequency without modulation.

I think this is already clear from HaiXiao's answer, but to re-iterate:

The modulation is down-spread which means that the average frequency is decreased when modulation is applied. This average decrease can be corrected through MULMOD. SPNU499B shows how to optimize MULMOD (equation 12 in chapter on PLL and OSC)

Best Regards,

Kevin Lavery