Other Parts Discussed in Thread: RM48L950, HALCOGEN
Hi,
Evaluation board : TMDXRM48HDK
emulator : XDS100v2USB
target : RM48L950.ccxml
o halcogen 3.6.0
o CCS 5.4.0
o Free RTOS 7.4.0 (utilisé à travers halcogen)
pb : not possible to flash software in RM48 any longer. Although it was working before.
Diagnostic messages are the following :
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CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0CortexR4:
GEL Output: Memory Map Setup for Flash @ Address 0x0CortexR4: Writing
Flash @ Address 0x00000000 of Length 0x00002CD8
CortexR4: Erasing Flash Bank 0, Sector 0
CortexR4: Finish Writing Flash @ Address 0x00000000 of Length 0x00002CD8
CortexR4: Writing Flash @ Address 0x000034D8 of Length 0x00000110
CortexR4: Finish Writing Flash @ Address 0x000034D8 of Length 0x00000110
CortexR4: Writing Flash @ Address 0x00008020 of Length 0x00007FF0
CortexR4: Erasing Flash Bank 0, Sector 1
CortexR4: Erasing Flash Bank 0, Sector 2
CortexR4: Finish Writing Flash @ Address 0x00008020 of Length 0x00007FF0
CortexR4: Writing Flash @ Address 0x00010010 of Length 0x000071D4
CortexR4: Finish Writing Flash @ Address 0x00010010 of Length 0x000071D4
CortexR4: Trouble Reading Register REG_ENDIAN: (Error -1044 @ 0xFFFFFF0E) The emulator reported an error. Confirm emulator configuration and connections, reset the emulator, and retry the operation. (Emulation package 5.1.207.0)
CortexR4: Trouble Setting Breakpoint with the Action "Terminate Program Execution" at 0x16970: (Error -1169 @ 0x16970) Unable to flush instruction cache. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.207.0) _________________________________________
After that the target does not answer with following error :
CortexR4: Error connecting to the target: (Error -1141 @ 0x0) Device is not responding to the request. Reset the device, and retry the operation.
If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package
5.1.207.0)
This message disappears when resetting the board + proc with the buttons on the board.
We tried several solutions (probe reset, system reset, processor reset) but nothing happens.
Here are some tests results for emulator connection :
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[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config
pathname(s)]------------------------------------
C:\Users\rarthaud\AppData\Local\.TI\693494126\
0\0\BrdDat\testBoard.dat
-----[Print the reset-command software
log-file]-----------------------------
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Aug 2 2013'.
The library build time was '22:12:43'.
The library package version is '5.1.207.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware
log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
-----[The log-file for the JTAG TCLK output generated from the
PLL]----------
There is no hardware for programming the JTAG TCLK frequency.
-----[Measure the source and frequency of the final JTAG TCLKR
input]--------
There is no hardware for measuring the JTAG TCLK frequency.
-----[Perform the standard path-length test on the JTAG IR and
DR]-----------
This path-length test uses blocks of 512 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
-----[Perform the Integrity scan-test on the JTAG
IR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
-----[Perform the Integrity scan-test on the JTAG
DR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End]
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Emulator config is :
Board Data File : auto generate
Emulator Selection : Only one XDS100 installed
JTAG nTRST Boot-mode : Disabled, Both EMU pins Hi-Z
Power-On-Reset Boot-mode : Disabled, Both EMU pins Hi-Z
TAG TCLK Frequency : fixed default 1.0 MHz
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Can you help ?
