Cache on 3137

Hello Chitra,

All current TMS570LS devices are based on a non-cached, tightly coupled memory architecture. If present, cache would be clearly indicated in the product datasheet.

Regarding your HDK question I will defer to one of my colleagues.

Best Regards,

Karl

Chitra,

Could you be more specific on the board you are using.

For TMS570LS3137 we have USB Stick or HDK board. Halcogen supports both.

Hi Karl,

We are currently using the MPU with the default settings on the TMS570LS3137, but assumed we could turn on caching between internal RAM and the ARM processor if needed.  The ARM Cortex-R4F TRM, Section 7.3, implies that we could set up memory regions as "write-through cacheable" or "write-back cacheable".  Is our assumption incorrect?

Thanks, Charlie Johnston

Hi Charlie,

The TMS570LS3137 does not have cache memory.  Cache memory is an optional feature for the Cortex R4/R4F.  The ARM TRM describes the superset of all features.  The system control register in CP15 can be read by software to confirm whether several optional features are implemented.

Even if cache memory were integrated on the TMS570LS3137, it would not be usable with TCM flash or SRAM, as both are already at the same level of memory hierarchy as processor cache.  The processor caches in the Cortex R4/R4F are only for accesses to level two memories (found on AXI master).

Best Regards,

Karl

Thanks, Karl.

This answers my secondary question.

Charlie Johnston.