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theoretical performance computation



Hi,

can you suggest some starting point (a document? a table somewhere?) to know more about the calculation of the theoretical performance of the processor and external devices (such as DMA)? For example how many CPU cycle are required to perform a specific operation?

Thank you

  • I am not awared that such a table exists.

    The answer to your question is very specific to the contiguous instructions and the status of the bus availability.

    For example, one instruction, from fetch to execute finish, roughly takes 7 cycles. However, with pipeline catch, it behaves like a one cycle instruction. However, if it is AXI bus load instruction, it will take roughly 25 cycles because the data is not ready. Again, it also depends on the MPU settings.

    Regards,

    Haixiao