DMA CHCTRL

Hello Matteo,

I have forwarded your question to one of our experts.  They should respond shortly.

Matteo,

This field controls the DMA read and write data size, address mode, trigger mode, etc. You have to configure it for any DMA transfer. There is a detailed table in TRM.

Thanks and regards,

Zhaohong

Hi Zahong,

my question was about the CHCTRL field of the g_dmaCTRL struct, not the CHCTRL register of the DMA.

Inside the dmaSetCtrlPacket function (HalCoGen generated) I can see that:

dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16U);

so seems that CHCTRL field sets the 16th bit of CHCTR register (CHAIN). From the manual this can be

• '0' for not channel chain
• '1' to chain with channel 0
• '4' to chain with channel 15

So must be leaved '0' if no channel chaining is used.

IAm I right?

Thank you

Matteo,

This is what I discussed in my post. You need to compare HALCoGen S/W with TRM.

Thanks and reagrds,

Zhaohong

I tried to attach a snapshot from the TRM. For some reason, It did not show up. let me try again.

Here it is.

I assume my last post contain the right answer.

Thank you

Done, sorry for the delay.

Thank you.