Hi,
I'm actually implementing a DMA data transfer from ADC FIFO (one sample a time). My DMA working setting is:
g_dmaCTRLPKT1.SADD = (uint32)&(adcREG1->GxBUF[0].BUF0); // source address
g_dmaCTRLPKT1.DADD = (uint32)&(adc_databuffer); // destination address
g_dmaCTRLPKT1.CHCTRL = 0; // channel control
g_dmaCTRLPKT1.FRCNT = DATABUFFER_SIZE; // frame count
g_dmaCTRLPKT1.ELCNT = 1; // element count
g_dmaCTRLPKT1.ELDOFFSET = 0; // element destination offset
g_dmaCTRLPKT1.ELSOFFSET = 0; // element source offset
g_dmaCTRLPKT1.FRDOFFSET = 0; // frame detination offset
g_dmaCTRLPKT1.FRSOFFSET = 0; // frame source offset
g_dmaCTRLPKT1.PORTASGN = 4; // port b
g_dmaCTRLPKT1.RDSIZE = ACCESS_32_BIT; // read size
g_dmaCTRLPKT1.WRSIZE = ACCESS_32_BIT; // write size
g_dmaCTRLPKT1.TTYPE = FRAME_TRANSFER ; // transfer type
g_dmaCTRLPKT1.ADDMODERD = ADDR_FIXED; // address mode read
g_dmaCTRLPKT1.ADDMODEWR = ADDR_INC1; // address mode write
g_dmaCTRLPKT1.AUTOINIT = AUTOINIT_ON; // autoinit (loop)
so I'm transferring ADC data of 32bit (in a uint32 buffer) even if my ADC is running at 8 bit. If I set the read size at 8 bit the FIFO mechanism seems to stop work (I assume the a 32bit access is required for the FIFO to work).
Is this correct or can I optimized somewhere?
Can you suggest the settings to move only the 8 meaningful bits in a 8 bit buffer?
Can this transfer be optimize accessing directly the ADC ram instead of using the FIFO mechanism?
Thank you
