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[Help] Unexpected Interrupt generated by hardware

Zhong Liu
Prodigy 100 points


Hi,

  I am working on an SCI DMA driver over RM48HDK.

  The only interrupt enabled is SCI RX DMA

    sciREG->SETINT = (1 << 17);			/* SET RX DMA */

 

I've check the run time memory also. Only DMA INT enabled.

But the weird thing is the hardware generate SCI high level interrupt which vector offset is 11u which is Receive Interrupt.

According to the TRM.

SCI Set Interrupt Register (SCISETINT) -- 17 SET RX DMA

Set receiver DMA. To enable receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.
0 Read: The DMA request is disabled.
Write: Writing a 0 to this bit has no effect.
1 Read and write: The DMA request is enabled for address and data frames

The receive interrupt will only triggered while DMA is cleared.

Would someone tell me what is wrong here?

Cause I enabled DMA for saving CPU resources. the unwanted interrupt will do something unexpected. It will lead to problem.

Another problem is,

I've setup DMA control packet correctly. While after HW Channel Enabled. The DMA worked

BUT the 1st byte was always missing. Anyone encounter that, please share some experience.

Thanks!

  • 0
    Prodigy 100 points

    Hi,

      Additionally, DMA should clear the HW Channel Enabled bit while DMA operation completed.

      I setup two DMA channel, 14d & 15d. 

    • 14d is for data transfer
    • 15d is for data receive   

      After DMA operation completed, I checked the memory.

      The data receive channel Enabled bit cleared as expected. But the transfer channel still enabled. This lead very odd consequence.

      dmaSetChEnable(channel , DMA_HW);

       The function can retrigger receive channel, but it will NOT trigger transfer channel successfully.

       Would TI employee give us some standard example for DMA programming. Or there are too many tips to work around.

       Thanks!

  • 0 in reply to Zhong Liu
    TI__Prodigy 710 points

    Thank you for your post.  One of our engineers will get back with you shortly.”

  • 0 in reply to Leo Huang1
    TI__Expert 4225 points

    Zhong,

    I re-assigned this thread from someone else ownership to my name since i did not see any response.

    Sorry for the delay in the response to this question.

    In the SCI TRM, you can see this statement:

    - In multiprocessor mode, the SCI can generate receiver interrupts for address frames and DMA requests
    for data frames. This is controlled by an extra select bit SET RX DMA ALL.

    - If the SET RX DMA ALL bit is set and the SET RX DMA bit is set when the SCI sets the RXRDY flag, then
    a receive DMA request is generated for address and data frames.

    - If the SET RX DMA ALL bit is cleared and the SET RX DMA bit is set when the SCI sets the RXRDY flag
    upon receipt of a data frame, then a receive DMA request is generated. Receive interrupt requests are
    generated for address frames.

    So, try SET RX DMA ALL to 1.  Looks like you have SET RX DMA ALL = 0 and you will have RX INT for address frame.

    If you observe missing first byte, then, try to enable HWCHANEA in DMA first, then, enable SCI.

    If your TX channel not completed, try to check your SCI DMA TX setting.

    if you can post your project, we can take a look at it.