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SDRCR value generated by HalCoGen

Emiliano Costagli
Prodigy 100 points
Other Parts Discussed in Thread: HALCOGEN

Hello,

I am using the Hercules RM48 HDK, and HalCoGen 03.06.00.

The value of VCLK3 is 80MHz, and, I am setting the following SDRAM parameters:

tRFC = 63ns

[...]

Refresh Period = 64ms

Refresh Cycles = 4096

The resulting value for RR (in register SDRCR) is 31, which means that my parameters have not been used (since it is less than 0x20, see SPNU503 section 17.3.4), and RR will be automatically set to (2 × T_RFC) + 1 = 11.

Is there any reason why HalCoGen is not using the following formula?

RR = fEMIF_CLK × tRefresh Period / ncycles

Thanks,

-Emiliano

  • 0
    TI__Mastermind 30845 points

    Hi,

    I have forwarded your request to our EMIF expert. Please stay posted.

    - forum support

  • 0
    TI__Guru**** 196346 points

    Hello Emiliano,

    SDRAM requires periodic refreshes to ensure the integrity of the data arrays. During an SDRAM refresh, accesses by the core are stalled until the refresh completes. SDRAM requires periodic refresh of all rows every 64 milliseconds. For SDRAM devices with 4096 rows, this gives a refresh cycle every 15.7us (64*1000/4096). If theEMIF clock is set to 80MHz, the refersh rate is 15.7*80=1250 rather than 31.

    You can use faster refersh rate than the value from the formula, but cannot be faster than the value given in the TRM (0x20). You know the refersh is to ensure the all rows inthe memory array are regularly read and written back.

    Regards,

    QJ

  • 0 in reply to QJ Wang
    TI__Guru**** 196346 points

    Hello Emiliano,

    The value (31) generated by HalCoGen is not correct. I will report to HalCoGen design team, thank you for finding the bug.

    Regards,

    QJ