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Question about HDK FET circuit on POR_RESETn / nTRST on page 7

Tom Major
Intellectual 260 points


I have a question about the HDK FET circuit on POR_RESETn / nTRST on page 7 of the schematic.

In this thread

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/226594.aspx?pi70900=1

it is stated that this is a "hardware workaround for an issue on pre-production silicon. The issue is fixed on production silicon"

Could someone from TI please confirm this again? We are designing a new board and I want to be sure. We will of course buy regular "production silicon" of this processor. We have a 10pin JTAG where there is no connection to nTRST.

So my main question is: Is it ok to just connect nTRST BGA D18 to a pull-up resistor. Will this do for both JTAG debugging and standalone operation?

Thanks, Tom

  • 0
    TI__Mastermind 30845 points

    Tom,

    Yes we can confirm that this has been fixed for production silicon.

    I am copying the HDK expert on this post.

    Also, do have a look at other threads regarding this topic:

    http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/245515.aspx

    Regards,

    Abhishek



  • 0 in reply to A Arora
    Intellectual 260 points

    Hello Abhishek,

    thanks for your answer. Unfortunately I don't understand the thread you linked, it seems to have nothing to do with nTRST, and it has no final answer.

    So could you or the HDK expert you mentioned please answer my main question:

    Is it ok to just connect nTRST BGA D18 to a pull-up resistor. Will this do for both JTAG debugging and standalone operation?

    Thank you very much,

    Tom

  • 0 in reply to Tom Major
    TI__Guru**** 198766 points

    Hi Tom,

    As the data sheet says, the nTRST pin is internally pulled down (a weak transistor is equivalent to a few tens of kohms). However, when using the JTAG port it is good practice to put an additional pull down at the connector level (ie the 10 k resistor) to prevent noise capture by the open connection, especially if long or running near a power supply. The transistor (Q2 on HDK) is not needed in your design.

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Intellectual 260 points

    Hello QJ Wang,


    thanks for commenting on this.

    So we will put a 10k pull-down resistor on nTRST input.

    The things that bothers me, since this signal starts with letter n, isn't this a active low reset signal? So pulling it low will held the JTAG circuitry in reset all the time, will it not? Will debugging still work with this?

    I also found in the reference manual, page 584: "Note: This bit is reset when Test reset (nTRST) is low."

    and

    page 771: "1. Make sure the device nTRST pin is high, since N2HET breakpoints are disabled whenever this pin is low. (Normally this is handled automatically when a JTAG debugger is attached)."

    As I wrote before, we are using a 10pin JTAG connector and therefore nTRST is not connected to the debugger.

    So, with all this active low hints I found, should it not be connected with a pull-up instead?

    Thanks,

    Tom

  • 0 in reply to Tom Major
    TI__Expert 4225 points

    Hi Tom,

    nTRST = 0 means in functional mode and nTRST=1 means in debug/test mode.

    In the TRM quote that you said, it means that when you connect the JTAG debugger, the debugger will drive nTRST=1 automatically. 

    The nTRST is pull low internally, but as QJ suggested, it would be good to pull low externally as well.

    Hope this help

  • 0 in reply to Henry Nguyen
    TI__Mastermind 30845 points

    Tom,

    Does the above answer your question?

    - Forum support

  • 0 in reply to Henry Nguyen
    Intellectual 260 points

    Hello Nguye,

    thanks for your answer. Still having trouble with the understanding.

    As I said, we have the standard 10 pin ARM JTAG connector where pin nTRST is not available. So the debugger *can not drive* nTRST to high.

    Does that mean that for instance we can not have N2HET breakpoints?

    page 771: "1. Make sure the device nTRST pin is high, since N2HET breakpoints are disabled whenever this pin is low. (Normally this is handled automatically when a JTAG debugger is attached)."

    What would happen if we supply a strong pull-up on nTRST instead of a pull-down?

    Thanks,

    Tom

  • 0 in reply to Tom Major
    TI__Expert 4225 points

    Hi Tom,

    Unfortunately, other test logic in the system will be resetting to proper state by nTRST active 0.

    So, i don't recommend to pull up high from the beginning.  You need to somehow pull nTRST low for "sometimes".

    Pull up high from the beginning will not work as it may cause un-resetting logic in some peripherals like NHET to issue an accidental debug request to halt the CPU.

    Few wild suggestions from my side (please note that these are wild suggestions and you need to determine best way for your system)

    1- Somehow, drive nTRST low on nPORST low.  Release it when NPORST is released it (basically same as nPORST).  But becareful to disable HW breakpoint in your peripherals like DMA/NHET/HTU in software production run because nTRST=1 will halt CPU if hw breakpoint condition in DMA/NHET/HTU is "true"

    2- Put a pull down initially.  Then, have a jumper or dip switch to set nTRST = 1 whenever you are ready to connect your debugger.

    Hope this helps you

  • 0 in reply to Henry Nguyen
    Intellectual 260 points

    Hi Nguyen,

    thanks.

    So we will stay with the external pull-down solution. If we need the HW breakpoints we will try to do this on the HDK.

    Tom