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PBIST OVER0 and RDS

Alan Day
Intellectual 920 points
Other Parts Discussed in Thread: TMS570LS3137

Hi all,

I'd just like to confirm that with OVER0 = 1 the PBIST ROM will load the appropriate settings so that I can test all RAM with all relevant algorithms with one single call of PBIST?

Secondly can you explain what Return Data Select (RDS) means, I've searched through the TMR for the TMS570LS3137 but cant find any explanation as to what it means.

Finally, I see there are registers for storing the first errors address (FSRA0&1) and data (FSRD0&1) while the counter ( FSRC0&1) registers are incremented when an error occurs and decremented when an error is processed, is there anyway of recording the address and data while the errors are found/being processed?

cheers,

alan

  • 0
    TI__Mastermind 30845 points

    I have forwarded your question to our PBIST expert. Please stay posted for a response.

    - Forum support

  • 0 in reply to A Arora
    Intellectual 920 points

    Hi, I have one further question, what memories do "RAM Group#" 33-58 represent?  They are mentioned in Table 2-15 but I can't see any further info.

    Also, just to clarify to test the Ethernet RAM I would need to write 1 to bits 23-25?

    cheers,

    Alan

  • 0
    TI__Intellectual 1480 points

    I'd just like to confirm that with OVER0 = 1 the PBIST ROM will load the appropriate settings so that I can test all RAM with all relevant algorithms with one single call of PBIST?

    Ans >>>Your observation is correct Secondly can you explain

     what Return Data Select (RDS) means, I've searched through the TMR for the TMS570LS3137 but cant find any explanation as to what it means.

    Ans >>> Return data select(RDS) indicates the memory data slice with in RAM group(RGS)  whose maximum width is generally 32 bits  

    Finally, I see there are registers for storing the first errors address (FSRA0&1) and data (FSRD0&1) while the counter ( FSRC0&1) registers are incremented when an error occurs and decremented when an error is processed, is there anyway of recording the address and data while the errors are found/being processed?

    Ans >> No there are no such registers

  • 0 in reply to Hari Pendurty
    Intellectual 920 points

    Is MSTDONE set to 1 after each error?

    It seems this is the case when reading the flow chart and the examples 1 & 2, as it suggests resuming the test after a failure.

    This leaves the completion of the PBIST test in an ambiguous state when failures are involved

    The only way I can know is with the use of RDS and RGS in the RAMT register, however what values would they have once a test has truly completed after previous errors?