We got an issue that on some our system it is running normal, but some system has the error that the CTCCOUNT is larger than the defination of ITCCOUNT. WE define element count as 1, frame count as 2000. Any idea about this?
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We got an issue that on some our system it is running normal, but some system has the error that the CTCCOUNT is larger than the defination of ITCCOUNT. WE define element count as 1, frame count as 2000. Any idea about this?
Hello,
can you send us a snippet of your codes that involves with how you configure your control packet initially and on the fly? are you using variables to compute frame count, element count and reinitialize DMA channel?
can you let us know what value you observe on CTCCOUNT when the system goes wrong?
it is a bit hard to guess unless we can have some visibility into what you are doing.
If you don't want the codes to be sent on public, please connect to me as a friend to establish a private connection and you can send the codes to me.
The code is in the moddle of modification. And we get more finding also. Maybe I can ask the question more straightforward: in which condition, the read-only CTCOUNT can be reset to the ITCOUNT. From the test I did, it seems changing the ITCOUNT and then resetting DMA does not work.
But our application, for the last frame, the data is not full frame since external gate signal decides it is last frame or not. Then when we start the new gate, even we do not have any DMA transfer, the CTCOUNT has vaule carried over from previous DMA operation.
Do I present the question a little clear?
Huichun,
"But our application, for the last frame, the data is not full frame since external gate signal decides it is last frame or not. Then when we start the new gate, even we do not have any DMA transfer, the CTCOUNT has vaule carried over from previous DMA operation."
To be honest, i have no idea what you are trying to do with the DMA in your application when i read the above lines from your writing. In DMA, user should not rely on CTCOUNT values in your application as the CTCOUNT is used as a scratch pad for the DMA kernel when switching priority between different channels.
Here is how CTCOUNT behaves:
The centralized DMA RAM fields for current transfer frame count, current element count, current src/dst address are intended for usage by the state machine to save channel context when channel arbitration occurs causing the current “incomplete” channel to be stalled. Incomplete channels means there are remaining frames to be transferred later on.
If the current DMA channel completes the current frame (not last frame yet) and there is no pending channel request with “higher” priority, then, there is no channel context saving. In this case, there is no RAM update for current frame count, element count, src/dst address.
If the current DMA channel completes last frame or block, then regardless if there is any pending channel request with higher priority or not, the current frame count, element count, src/dst address of this channel in RAM will not be updated; there is no channel context save because channel “completes” all of its frames or block.
If there is only one channel enabled in the DMA, the channel will start and complete without any interruption from other channel. In this case, the current frame count, element count, src/dst address of this channel in RAM will not be updated because there is no channel context saving due to no arbitration.
To inspect the amount of transfers has been done, it is recommended to use FTC flag, HBTC flag, BTC flag or LFC flag and their associated interrupt and offset register.
Hopes this help you!