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RM4x - using MPU for safety critical application

Shing Lee
Intellectual 545 points

Hi, We are currently developing a system using a single RM46 micro which will contain codes to handle both safety critical and non-safety related features.  We would like to encapsulate and protect the safety code segment and the RAM variables used by the safety codes. 

1. Do you have any application notes available on how it can be done?  My thought is to use the MPU but presumably I need to modify the link map file (sys_lnk.cmd) to tell the linker explicitly where to place the safety code and its associated variables?  How to structure the files witin Code Composer so that the object files under safety control module can be frozen and not affected by any changes to other parts of the system?

2. As a general question, do we also need to protect the peripherals and I/O used for safety application as well?  Can it done in the RM46 and how?

3. Are there any application notes on how best to integrate the TI safety library codes to the system which runs under say FreeRTOS/SafeRTOS?

4. Are there any app notes detailing how to use the features available in the RM46 (as well as the safety library software) to fulfill UL1998 class 2 requirement?  A clause by clause checklist will be really useful.

Thanks

  • 0
    TI__Mastermind 30845 points

    Shing,

    There are multiple different mechanisms implemented in the Hercules family that help in partitioning and executing safety code and non safety code in one CPU. The MPU is surely a key mechanism for this. Not only does the Cortex R4 CPU have an MPU, but bus masters like the DMA, and transfer units have dedicated MPUs as well so as to limit their access.

    The intended use of MPU regions is not just limited to RAM space, but also peripherals. One can limit the access of non safety critical code to only non safety critical peripherals. You should be able to take advantage of the 12 MPU regions in Cortex R4 in the RM46x.

    I don't believe we have a specific app note that directly targets what you are looking for. Let me check and get back to you.

    Here's a related app note that might be of use:

    http://www.ti.com/litv/pdf/spna120

    Regards,

    Abhishek

  • 0 in reply to A Arora
    TI__Mastermind 23000 points

    Here is another app note, this time from ARM, that may be of use though it is targeting cached R4/R5 instead of with TCM:  http://infocenter.arm.com/help/topic/com.arm.doc.dai0296a/DAI296A_CortexR_Memory_protection.pdf

    Regarding UL1998, we have some work ongoing and hope to be able to share it before the end of the year.

    Regards,

    Karl

  • 0 in reply to KGreb
    Intellectual 545 points

    Thanks Abhishek, Karl,

    Much appreciated for your assistance.  Any more related app. notes would be welcome.  I am intrigued by Karl's statement regarding UL1998, it would be greatly appreciated if such info can be shared with us as early as possible.  Since we are working on a very tight project timescale, we would like to avoid any mishap and misunderstanding in our system architecture and design approach.  We are happy to sign any NDA if needed.

     

    Regards

    Shing

  • 0 in reply to Shing Lee
    TI__Mastermind 30845 points

    Shing,

    Once finalized we will make this document available to you. In the mean while I would recommend to use the respective Hercules safety manual and analysis reports. Many of the UL 1998 requirements would get fulfilled by using the recommendations in our safety manual.

    Regards,

    Abhishek

  • 0 in reply to A Arora
    TI__Intellectual 1485 points

    Here is a link to the Hercules MCU IEC 60730 and UL 1998 white paper that has just been released:

    http://www.ti.com/lit/wp/spny005/spny005.pdf