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nRST operation

Richard Burke
Expert 1910 points


Hello,
Could you please clarify operation of the nRST pin. From what I can tell from the datasheet, nRST is pulled high internally (with approximately 33K) and can be driven low by the processor i.e. it is open drain.

If another device wants to perform a warm reset, it should drive nRST low. However I assume that it cannot drive nRST high following a reset because then there would be a potential clash when the processor is driving nRST low following activation of nPORRST. Instead the pullups (internal and external) must be relied upon to take nRST high. Is this correct?

Would there be a problem if nRST was driven high provided that it was tri-stated before nPORRST was activated?

Thanks,

Richard

  • 0
    TI__Mastermind 22375 points

    Richard,

    Because of nRST structure (Open drain) it is necessary to use an open drain circuitry to drive it from outside.

    Any internal reset as PLL, oscillator, watchdog... reset condition will drive the pin to 0. If you have a strong driver to 1 externally, it may damage the nRST pin.

    Let me know if I've answered your question.

  • 0 in reply to Jean-Marc Mifsud
    Expert 1910 points

    Hi Jean-Marc,
    Thanks for your quick response but could you please clarify:

    Are you saying that a PLL failure or oscillator failure of the processor will actually drive the processor's nRST pin low?

    Is this for the 8 VCLK cycles refererred to in the datasheet? By my calculation for VCLK = 100 MHz, this is 80 ns.

    Regards,
    Richard.

     

  • 0 in reply to Richard Burke
    TI__Mastermind 22375 points

    Richard,

    Here is an extract from the TRM concerning the nRST signal.

    The table lists all possible internal reset condition that will be visible on the nRST pin.
    The nRST is an open drain bidirectional pin.

    Please let me know if this clarify your question.

  • 0 in reply to Jean-Marc Mifsud
    Expert 1910 points

    Hi Jean-Mark,

    Thanks for that - my question is answered.

    I have to admit that I am a little surprised that the processor drives the nRST pin low for an internal condition. I guess the time is so short that it would not normally affect anything else to which that pin might be connected.

    Regards,

    Richard