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ADC readings lower than expected



Hello,

My adc readings for the TM4C126GH6PM (with 3.3v vref) seem to be some percentage lower than what I should be getting. I'm also seeing other odd behavior. First, here is my init code for the adc and some code from where I read:

// Initialize the ADC
GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3);
GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2);
SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
ADCSequenceConfigure(ADC0_BASE, 2, ADC_TRIGGER_PROCESSOR, 0);
ADCSequenceStepConfigure(ADC0_BASE, 2, 0, ADC_CTL_CH0);
ADCSequenceStepConfigure(ADC0_BASE, 2, 1, ADC_CTL_END | ADC_CTL_IE | ADC_CTL_CH1);
ADCIntEnable(ADC0_BASE, 2);
ADCIntClear(ADC0_BASE, 2);
ADCSequenceEnable(ADC0_BASE, 2);

uint32_t seq_buf[4] = {0};

ADCProcessorTrigger(ADC0_BASE, 2);
while(!ADCIntStatus(ADC0_BASE, 2, false));
ADCSequenceDataGet(ADC0_BASE, 2, seq_buf);
ADCIntClear(ADC0_BASE, 2);

return seq_buf[1];

As you can see I have two adc channels being configured in steps in sequence 2.

If i measure 1.5 volts at the adc input, i get about 1400 counts from the adc. With a 3.3v vref and 12 bit adc I should be getting about 1800 counts for 1.5 volts.

In my application, I take one adc sample every 250 ms. If I plot the data I get something that looks like a sawtooth pattern:

Could this be a timing issue? I tried adding large delays before reading from the adc and saw no change.

Thanks,

-Brandon

Edit: I previously stated that I saw a slight sawtooth pattern in my samples, but that is actually normal for my application. My setup was incorrect when I initially checked it.

  • MCU manual for our LX4F device (predecessor of yours) reveals ~500 max series, "analog source resistance."  Cannot find your characterization of your input voltage source.  (Rs is defined/detailed under electrical specs - manual rear)

    We find it helpful to initially apply mid-scale, stable, low impedance voltage source as ADC signal input.  Any signal variations - at this initial stage - complicate your analysis.  Also usually proves helpful to change to a 4 or 8 step sequence - locked to that same channel.  (this reveals any time instability - w/in your introduced signal or the ADC internal network) 

    There is some, "channel to channel" interaction - you may adjust the input levels of any other channels (or remove all of them) to see if this "contributes" to your perceived measurement error.

    As always - proper powering of Vdda (we employ a small ferrite bead & filter cap @ Vdda) and Vddgnd prove helpful... When scoped - Vdda should be proper & rock-stable...

  • That seems to be what tripped me up. The output resistances of our sources are much higher than 500 ohms. I did a quick test with a low resistance voltage divider and the adc was returning the correct values. We just have to stick some buffers in between. 

  • Thank you, Sir.  Jelly bean op-amps - wired as voltage followers - may well serve that purpose...