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NHET: execution time of SUB, ADD & friends

Jan Nárovec
Intellectual 410 points

Hello,

I use the following instruction for some calculation and storing it's result:

SUB { src1=R, src2=T, dest=NONE, rdest=REM, remote=SOME_LABEL, data=0 }

Now, what is the execution time of mentioned instruction? I think it doesn't fit into any line of Table 20-56 in SPNU499b. From the HET simulator, I have figured out that it is one-cycle instruction, am I right?

Thank you,

  Jan

Edit: the MOV32instruction in the following pair of instructions should take – according to the Table 20-63 in SPNU499b – one cycle, but the HET IDE shows, that it takes two cycles. I guess, that the HET IDE is right, as the ECMP instruction immediately follows the MOV32.

MOV32 { remote=LABEL, type=REGTOREM, reg=R, z_cond=ON, data=DUMMY_DATA, next=LABEL };
LABEL ECMP { hr_lr=HIGH, en_pin_action=ON, pin=PIN1, action=PULSELO, reg=A, data=DUTY_CYCLE };

  • 0
    TI__Prodigy 710 points

    Thank you for posting on the E2E forum. One of our engineers will get back to you shortly

  • 0 in reply to Leo Huang1
    TI__Expert 4225 points

    Hi Jan,

    sorry for the late response.  

    Please see picture below.  Your instruction rdest=REM, so it takes 3 cycles.

    for the MOV32, your configuration should take 1 cycle.  be careful because your next is also your next instruction.

    hope this helps.

  • 0 in reply to Henry Nguyen
    TI__Guru 68920 points

    Henry, Jan,

    There is an architectural restriction that is not specific to MOV32 - which explains why the instruction is taking 2 cycles.

    It is because it is modifying the data field of a remote address, and this remote address is also the next address.

  • 0 in reply to Henry Nguyen
    Intellectual 410 points

    Thank you for your answer. You say that the SUB instruction - according to the highlighted line of Table 20-56 - takes three cycles, but my understanding of mentioned table is, that conditions in all columns has to be met. And because src1=R and not REM/REMP, I couldnt assign the SUB instruction to any line of table 20-56.

  • 0 in reply to Jan Nárovec
    TI__Guru 68920 points

    Jan,

    Assuming that the rem != next, then it seems closest to either the 1st or the 3rd line in the table.

    In the first line there is 1 write back to memory - which in some sense matches this case because you're not writing back to IMM just REM.   Whereas line 3 assumes you're writing back to IMM and REM and it's an extra cycle because of this.

    I think this has come up before - that the table doesn't fill all the possible combinations.  I'll do some digging to see what I can find.