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C compilator and TMS570LS3137 bug DEVICE#B064

Jiri Dobry
Expert 1810 points

Hello.

Do you have any idea how to use workaround for bug DEVICE#B064 when we use "C" compiler?

Compiler use LDM/STM pair of instruction frequently to manipulate with data.  And we don't have any chance to control it.

For example let have this snipplet. If we place "a" into external memory we have problem. And we don't know about it in most cases.

struct test {
 int x1; int x2; int x3;  int x4;
};
struct test a; // I can't be sure if it is 64-bit alligned address
struct test b;
void testFn(void) {
     a = b; // use pair of LDM/STM instructions
}

  • 0
    TI__Mastermind 49120 points

    Hello Jiri,

    We have identified that a write to external memory using a store-multiple instruction causes an issue regardless of whether the first address is 64-bit aligned or not. We don't have any suggested workaround for this other than not using a store-multiple instruction to write to external memory. The errata documents are being updated to reflect this as well.

    Our compiler team is working on a patch to provide a file-based as well as a function-based switch (pragma) to completely disable using a STMxx instruction in the compiler output for user-selected files/functions.

    This switch need not be enabled when burst write accesses occur to internal RAM. I will confirm the date for availability of a beta compiler update and update this post.

    Please let me know if you have any questions.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Expert 1810 points

    Nice, but it complicate use 3rd party compilers. And we don't plan to use TI ComposerStudio compiler.
    Do you have any plan to fix it on silicon? 

  • 0 in reply to Jiri Dobry
    TI__Mastermind 49120 points

    Hi Jiri,

    There are discussions ongoing on a plan to fix the silicon. We will certainly let you know once a plan is finalized.

    I agree that this complicates issues for customers working with 3rd party compiler vendors. You will need to push these vendors for a patch similar to that planned for the TI codegen tools.

    Regards, Sunil