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HalCoGen RM48 Selftests Bugs

Other Parts Discussed in Thread: RM48L952, HALCOGEN

Today, I observed some problems with HalCoGen and RM48L952 with selftests enabled:

- Enable FMCBUS2 Error Check in HalCoGen: The function  fmcBus2Check needs a power on reset to work properly

- Enable ESRAM ECC Check in HalCoGen: The function checkRAMECC has some bugs:

The following line in checkRAMECC is...

if(!(((tcram1REG->RAMERRSTATUS & 0x1U) == 0x1U) && ((tcram1REG->RAMERRSTATUS & 0x1U) == 0x1U)))

and should be

if(!(((tcram1REG->RAMERRSTATUS & 0x1U) == 0x1U) && ((tcram2REG->RAMERRSTATUS & 0x1U) == 0x1U)))

In the same function a short delay is needed in order to pass the RAM ECC selftest:

    u32Cnt = 2;
    while( u32Cnt > 0)
    {
        u32Cnt--;
    }

    /* Force a single bit error in both the banks */
    tcramA1bitError ^= 1U;
    tcramB1bitError ^= 1U;

Without the delay the selftest will always fail. A reason for this could be caching?!

Could you please check this and confirm me that issue?

Thanks.