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Tiva I2C Master CLK Mini Pulse Issue

Jonathan Chiou
Prodigy 80 points
Other Parts Discussed in Thread: TM4C123GH6PM

Hello, every one

I use the TM4C123GH6PM Chip. 

I found CLK bug that caused my SDA Bus is pull Low from Slave drive

Because the slave drive is waiting the ninth pulse, but master finished to send nine pluses

Where the small pulses only 250ns, so the slave did not catch

I use the MCU Master I2C Interrupt Control


Is there any way to solve a small pulse? 

thanks,

  • 0
    Guru 117855 points

    Am somewhat active this/other ARM forums - cannot readily recall such, "abbreviated, midstream pulse" as past, reported issue...

    Now your top line display (appears to be I2C Bus Decode) indeed shows agreement w/SDA (line 2) and first 8 clocks. (SCL, line 3)  Thus - even though the 7th clock pulse in this sequence is "narrow" - the decode appears to have worked.  It is apparent that this "narrow," 7th clock pulse is properly spaced/placed - but clock pulse 8 appears too soon.  (although it returns to proper width)

    You've not detailed the frequency of this behavior - nor whether this narrow clock pulse occurs "only" w/in bit 7 - and/or when other data values are transmitted.  This may prove useful.

    Further - does this effect occur in the identical manner - across other boards - and w/other Slave devices?  Do you employ "real" pull-up Rs and is anything else (software-wise) occurring during this I2C transaction - which may impact the proper I2C operation?