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How to setup BTC interrupt during MibSPI DMA

Chris_2013
Prodigy 30 points

Hi All,

I need help with configuring the MibSPI3 to raise the BTC interrupt after every DMA TX. I enabled the BTC during TX DMA but no interrupt was received. Please see my code below:

mibSpi3DmaTx[0].SADD      = (uint32) buffer;
mibSpi3DmaTx[0].DADD      = (uint32) &(mibspiRAM3->tx[4].data);
mibSpi3DmaTx[0].CHCTRL    = 0;
mibSpi3DmaTx[0].FRCNT     = 61;//Transfer Group size for TG02
mibSpi3DmaTx[0].ELCNT     = 1;
mibSpi3DmaTx[0].ELDOFFSET = 4;
mibSpi3DmaTx[0].ELSOFFSET = 0;
mibSpi3DmaTx[0].FRDOFFSET = 0;
mibSpi3DmaTx[0].FRSOFFSET = 0;
mibSpi3DmaTx[0].PORTASGN  = 4;
mibSpi3DmaTx[0].RDSIZE    = ACCESS_16_BIT;
mibSpi3DmaTx[0].WRSIZE    = ACCESS_16_BIT;
mibSpi3DmaTx[0].TTYPE     = FRAME_TRANSFER ;
mibSpi3DmaTx[0].ADDMODERD = ADDR_INC1;
mibSpi3DmaTx[0].ADDMODEWR = ADDR_OFFSET;
mibSpi3DmaTx[0].AUTOINIT  = AUTOINIT_ON;

dmaEnableInterrupt(DMA_CH6, BTC);
dmaReqAssign(DMA_CH6, MBSPI3_CH0_TX_DMA_REQ_LINE);

dmaSetCtrlPacket(DMA_CH6,mibSpi3DmaTx[cs]);


dmaSetChEnable(DMA_CH6, DMA_HW);
mibspiREG3->DMACTRL[0] =
      14 << 20 //set DMA RX request lines
    | 15 << 16 //set DMA TX request lines
    | 0x8000C000  //enable transmit and receive DMA, disable after 1 transfer
    | 2 << 24 //TG02
    | 0 << 8; //set initial transfer count

mibspiTransfer(mibspiREG3, group);

xSemaphoreTake(fram_tx_sync, portMAX_DELAY);

Thanks in advance

  • 0
    TI__Mastermind 22715 points

    Chris,

    I see three options to use DMA with MibSPI.

    (1) Use DMA with SPI (MibSPI compatibility mode). In this case, DMA moves data between memory and SPI TX/RX register. Two DMA channel is required. A DMA BTC or HBC interrupt can be generated after the block or half block transfer. You can see more information in this thread.

    http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/301494.aspx

    (2) Use DMA with MibSPI mode. One Rx/Tx buffer per transfer group. Two DMA channels are required per transfer group. This is what described in the TRM. In the attached example, three transfer groups are enabled with 6 DMA channels. When the transfer group is complete, a MibSPI interrupt will be generated.

    6761.mibspi_dma16a.zip

    (3) Use DMA with MibSPI mode. Multiple Rx/Tx buffers per transfer group. When the transfer group is complete, a MibSPI interrupt will be generated. Then the user can read the received data and write the new transmit data to MibSPI RAM with DMA. The advantage of this option is that DMA can do burst transfer (fill multiple buffers in the MibSPI RAM) which makes the memory (RAM) access more efficient. It is much more complicated. I would not recommend it unless you are transferring a lot of data continuously (such as write to a graphics display with SPI interface).

    Thanks and reards,

    Zhaohong