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HalCoGen Not generating sys_svc.asm file

jeff donner
Prodigy 75 points

Other Parts Discussed in Thread: HALCOGEN

Using HalCoGen version 03.06.00 with micro TMS570LS1227PGE

On the Interrupts tab I enable the SVC interrupt and generate the source code.

I am surprised that the sys_svc.asm file isn't created by the tool.

The sys_intvecs.asm does a .ref of _svc, so I think the tool should be generating the file.

  • 0
    TI__Guru 69070 points

    Jeff,

    I'll check on this - but I think the most that the HalCoGen tool could do is to create a stub.

    You pretty much need to write your own handler for SVC calls.

    If you don't mind me asking - what are you planning to use the SVC call for?

    We do support software triggered IRQs and that might be easier to use depending on your needs.

  • 0 in reply to Anthony F. Seely
    Prodigy 75 points
    to enable/disable the IRQ and FIQ interrupts.  here is my sys_svc.asm code (below).  I was told by another s/w guy that this is the only way to do it.
     
        .global _svc
        .global _swi_enable_fiq
        .global _swi_disable_fiq
        .global _swi_enable_irq
        .global _swi_disable_irq   
        .global _swi_enable_fiq_irq
        .global _swi_disable_fiq_irq
     
    HIGHEST_SWI    .equ  0x06
    FIQMASK        .equ  0x40
    IRQMASK        .equ  0x80
     
        .asmfunc
     
    _svc:
     
        stmfd  sp!,  {r0-r12,lr}
        ldr r0,[r14,#-4]        ; Get SWI Instruction
        and r0, r0, #0xff        ; Look at lower 8 bits of SWI Number Only
        cmp r0, #HIGHEST_SWI        ; Check for SWI out of Range
        bhi _swi_exit            ; Exit Immediately if SWI out of Range
        mrs r1, spsr            ; Get SPSR for SWI's that change PSR
     
        ldr pc,[pc,r0,lsl#2]        ; Dispatch Instruction
        mov r0,r0            ; Exactly 1 Word Between Disp. Instr and Table
        .word    _swi_enable_fiq        ; SWI 0x00 - Dispatch Table Begins Here 
        .word   _swi_disable_fiq    ; SWI 0x01
        .word   _swi_enable_irq        ; SWI 0x02
        .word    _swi_disable_irq    ; SWI 0x03
        .word   _swi_enable_fiq_irq    ; SWI 0x04
        .word    _swi_disable_fiq_irq    ; SWI 0x05
       
    _swi_disable_fiq
        orr r1, r1, #FIQMASK
        msr spsr_cxsf, r1
        b   _swi_exit
           
    _swi_enable_fiq
        bic r1, r1, #FIQMASK
        msr spsr_cxsf, r1
        b   _swi_exit
     
    _swi_disable_irq
        orr r1, r1, #IRQMASK
        msr spsr_cxsf, r1
        b   _swi_exit
     
    _swi_enable_irq
        bic r1, r1, #IRQMASK
        msr spsr_cxsf, r1
        b   _swi_exit
     
    _swi_disable_fiq_irq
        orr r1, r1, #(FIQMASK|IRQMASK)
        msr spsr_cxsf, r1
        b   _swi_exit
     
    _swi_enable_fiq_irq
        bic r1, r1, #(FIQMASK|IRQMASK)        ;I and F bit be cleared
        msr spsr_cxsf, r1
        b   _swi_exit
    _swi_exit:
            ldmfd  sp!,  {r0-r12,pc}^
     
        .endasmfunc
     
  • 0 in reply to jeff donner
    TI__Guru 69070 points

    Hi Jeff,

    Got it.  If I understand then you've got the answers you need but you think we should take this as an enhancement request for HalCoGen - is that right?   I'm going to file an enhancement request since that seems like the correct thing to do.

    I checked HalCoGen and did find that the FreeRTOS projects do generate a SWI handler because now FreeRTOS supports setting tasks to execute in user mode and the SWI handler becomes necessary.    [for projects that stay in System mode, you don't need to use a SWI in order to enable / disable interrupts]...    So you might be able to use one of the FreeRTOS projects if you need something from HalCoGen right now.