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RM48 ECC test

Lukas Kuenzi
Intellectual 400 points
Other Parts Discussed in Thread: RM48L952, HALCOGEN

I want to test the ECC functionality of the RM48L952. I used the Ram ECC test like "checkRAMECC" provided by HalCoGen. I see that single and double bit errors are recognized correctly. Now I want to generate an interrupt in the case of a single or a double bit error.  In HalCoGen  I enabled the ESM channels 26 and 28 for single bit errors. According to SPNS177 double bit errors are mapped to ESM Group2  channel 6 and 8 and/or ESM Group3 channel 3 and 5. I'm confused. On which channels are they mapped?

But I do not receive an interrupt on a single bit error detection. I think the "esmHighInterrupt" should be called. But this is not the case.

In the case of double bit error detection the dabort is called. Why do I receive a data abort and not the esmHighInterrupt interrupt?

What I'm doing wrong? Do I have to set something else?

Regards,
Lukas

  • 0
    TI__Mastermind 23000 points

    Hello Lukas,

    As the ECC controller is built into the CPU, a detected fault directly generates an abort in the CPU in order to react in minimum time.  The ESM group 3 mapping of the error is provided so that you can generate an error pin action in addition to the abort.

    Group 2 channel 6 and group 2 channel 8 are for additional uncorrectable faults detected in the SRAM wrapper.  I believe these are triggered by faults in the redundant address decode.

    Regards,

    Karl

  • 0 in reply to KGreb
    Intellectual 400 points

    Hi Karl,

    Thank you for the information. Is this also true for the flash ECC? But how can I force the CPU to generate an interrupt for single bit error detection in flash or ram? This should be possible with the ESM module?!

    Regards,

    Lukas

  • 0 in reply to Lukas Kuenzi
    TI__Mastermind 23000 points

    Hi Lukas,

    The scheme is the same for all TCM memories, which includes flash and SRAM.  

    If you wish, you can disable correction using the second auxiliary control register inside the CPU.  In this case a single bit ECC fault will also generate an abort inside CPU.  For a fault on instruction fetch you will see a prefetch abort, for data fetch a data abort.

    It is also possible to use the ESM to generate an external error indication and/or interrupt on a single bit error.  The interrupt is not recommended as it is redundant to the abort and occurs at slower speed.  The option remains as a compatibility bridge from older generation products where the ECC was not integrated into the CPU.

    Regards,

    Karl

  • 0 in reply to KGreb
    Intellectual 400 points

    Hi Karl,

    Ok, Thank you for your help.

    Regards,

    Lukas