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RM48L952 cpu self test and sci receive

Luděk Hezina
Prodigy 140 points
Other Parts Discussed in Thread: RM48L952

Hi,

I have RM48L952. I'm trying implementing max 100 ms iteration of cycle which starts by externa events and comunikate over sci.

One iteration consist:

1 - gather some data

2 - transmit over sci in blocking mode

3 - parse received packet on sci ( receive is in interrupt mode or dma)

4 - run cpu self test over all 24 regions

5 - wait for external event whitch start new iteration

Points 1 - 3 is certainly less then 50ms. And communication baudrate is 115200  Receive on sci missing some data regardless on mode of operation (interrupt or dma) and receive by polling mode is not an option because this violates 100ms maximum period of one cycle.

I think that in spu self test dma or receiveinterrupt don't work. Is that true? And possibly how can I this evade?

Thanks in advance,


Luděk Hezina

  • 0
    TI__Guru 68950 points

    Luděk,

    I think the issue is probably that you cannot use interrupts or the DMA to the RAM while the CPU is in self test mode.

    The CPU is isolated in self test mode since it's logic bist based, and you can see from the figure below that the path that the DMA needs to take to get to the CPU would go through the CPU:

    There is the option to break the CPU self test into smaller segments so your system can be responsive to tighter deadlines.  Can you try this approach to keep the SCI Comms from overflowing?