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Undefined entry on enable CPU event bus

Pablo Cottens
Genius 3020 points


Hello,

Whenever the bootloader reaches the _coreEnableEventBusExport_ function it  marks the  instruction as an undefined entry.

Here's the code for it. There is nothing wrong with it. whenver I load a different example it works perfectly, but when I try another then it just goes to an undefined entry.

    .def     _coreEnableEventBusExport_
    .asmfunc

_coreEnableEventBusExport_

        mrc   p15, #0x00, r0,         c9, c12, #0x00
        orr   r0,  r0,    #0x10
        mcr   p15, #0x00, r0,         c9, c12, #0x00
        mrc   p15, #0x00, r0,         c9, c12, #0x00
        bx    lr

    .endasmfunc
  • 0
    TI__Mastermind 22375 points

    Pablo,

    Out of context, it is difficult to see what could be wrong.

    So let me ask some questions.

    1] Does the Core register initialization done correctly?
    2] Does the Stack initialization done correctly?
    3] Within the _coreEnableEventBusExport_routine, can you check the value of LR and see if it is pointing to the return address.

    Could you share more of your code to see your bootloader structure?

  • 0 in reply to Jean-Marc Mifsud
    Genius 3020 points

    Hello,

    Sorry for such a vague question, but after some time away from the PC I found out that there was an instruction missing. The uC went into system mode, when it should've gone into supervisor mode.

    I was able to fix it.

  • 0 in reply to Pablo Cottens
    TI__Mastermind 22375 points

    Pablo,

    That is a good news. Can you than close this thread?

  • 0 in reply to Jean-Marc Mifsud
    Genius 3020 points

    I would like to ask another question before that.

    When I'm reading ESMSR3 to check for any grouo 3 errors, it goes into a data abort excpetion.

    My code:

        if (ESMReg->ESMSR3) { /*If this happens the system must not continue with the boot process*/
        while(1);
    }

    The generated asm:

    00000d50: E59FC168 LDR R12, $C$CON5

00000d54: E59CC000 LDR R12, [R12]

00000d58: E35C0000 CMP R12, #0 00000d5c:

0A000000 BEQ $C$DW$L$bootAfterReset$37$E

    After instruction @0x00000D50 I check that R12 is loaded with the correct address (0xFFFFF520), but when it executes the instruction @0x00000D54 it generates an interruption.

    Also the value @0xFFFFF520 = 0x0, which indicates that no group 3 errors occurred.

    The uC is in supervisor mode M[5..0]=10011 of CPSR. About this error I really have no idea what's going on.

  • 0 in reply to Pablo Cottens
    Genius 3020 points

    Found the error. Reading from 0x0FFFF520 instead of 0xFFFFF520