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Multiple peripheral configuration on a single pin

Rakshit Ramesh
Intellectual 670 points
Other Parts Discussed in Thread: TLC5940

I'm using the Tiva C Series Launchpad .
I require  the SSI0 Base SSI module to communicate with my SIPO device .
The SIPO device at times requires extra clock pulses from PA2 which is defined as  GPIO_PA2_SSI0CLK .

Is it possible to define the pin PA2 as   ( GPIO_PA2_SSI0CLK)    & as a GPIO as well ?
If not ,what is the alternative ? 

Here is what I have attempted :-

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinTypeGPIOOutput(SCLK_PORT, SCLK_PIN);

&

SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA2_SSI0CLK);

 

Whatever I have done above hasn't worked and I'm not getting the extra clock pulse .
 

  • 0
    Guru 117855 points

    This looks like an ideal marriage between MCU and 2 input logic-gate - said gate's output driving your SIPO's clock.  Appears that "or" will achieve your function - provided that gpio which drives 2nd logic input returns to "0" when not active.

    This method enables as many "extra" pulses (to include zero/none!) as you may require - and causes no disturbance to the MCU's "normal" SPI operation.  (provided you excite your gpio outside of SPI's operating time-frame)

    More risky - and demanding test/measure - would involve change of that pin's PinType() & PinConfig() - prior to each/every set-up/config.  Note that the code you show fails to exercise that "dual step" configuration...  By "risk" - live, on the fly - re-config of any pin serving as "clock" often proves less than, "best practice."  (and - in some demanding apps - is strictly, Verboten!)

  • 0 in reply to cb1_mobile
    Intellectual 670 points

    Using a logic gate for my purpose would require me to include another IC into my PCB .
    Thank you for the idea ,but unfortunately i have very little space to expend .

    I had actually wanted to mention the "on the fly" method in my post ,but thought it would be too naive  ,nevertheless ,neither did that work ,(to provide an extra clock pulse) .


     My SIPO device  is  "TLC5940 Led driver" .
    Here are some useful links 
    1 . Datasheet  -  http://www.ti.com/lit/ds/symlink/tlc5940.pdf
    2. Programing  flowchart -  http://www.ti.com/lit/sw/slvc106/slvc106.pdf

    Notice timing diagram on page 12 of the datasheet ,SCLK pulses 192 times to clock in GS bits and finally pulses for the 193rd time without passing any bits .
    Is it possible to pass in a dummy bit (or even the next cycle GS2 MSB1 bit) just to obtain another pulse ?


     

  • 0 in reply to Rakshit Ramesh
    Intellectual 670 points

    I would like to report that I got my SIPO device (TLC5940 ) to work .(LEDS behave as expected)
    Although I am not sure if MOSI device is actually injecting an extra clock pulse .
    I feel it is immaterial now  ,now that all expected behaviour from the TLC is obtained(PWM fading ,led selection ,etc)

    I would like to mention a strange phenomenon ,assuming that the Master is actually injecting an extra clock pulse  ,
    :-

    I had only initialized the SSI0 module and hadn't initialized PA2 (SSI0Clk) as GPIOOutput .
    I still was able to write to the GPIO PA2 which was SSI0Clk .(Assuming i am indeed getting the extra clock ,evident from parallel output from my SIPO) .

    I will scope PA2 ASAP (Not anytime soon though ,I have my exams going) and return with the result .

    As usual ,thank you cb for your quick ,gracious ,and intelligible help .  

  • 0 in reply to Rakshit Ramesh
    Guru 117855 points

    Rakshit Ramesh said:
    As usual ,thank you cb for your quick ,gracious ,and intelligible help .  

    Be still my heart!  Speaking to gracious - that would be you mon ami - merci beaucoup.  (3rd grade, NYC public, grade school teacher who tormented me {prior to ADHD being officially invented/recognized} should see me now...or not)  (Reality - 1 of those 3 kindnesses is usually my best reward...)

    I try to recommend/suggest devices which my group have actually used - and confirmed.  And - as you state - size is important.  And - this vendor's "NC7SZ57" provides such a gate - and the entire IC is 08-05-like, in size.

    When you do find time/interest to scope - I'd look closely for any "glitch" as you reconfig the SPI_CLK to/from GPIO.  Again - as it is a controlling clock - you may wish to include a pull-up/down just in case that pin transitions to hi-Z - which is usually unwelcome at any clocked input, downstream.  And - any such reconfig of operating clock-line driver - on the fly - will direct (often unwanted) attention upon your design...  Gate answers/protects...