SPI programming

Hello Srini,

Can you paste your code showing how you configured the SSI pins? If you aren't seeing any clock signals there maybe something wrong there.

Sheldon

Hi Sheldon,

 Here is my code which configures SSI and sends three bytes. I have set the system clock to be 80 MHz (in a separate function before calling this function.

{
uint32_t pui32DataTx[NUM_SSI_DATA];
uint32_t pui32DataRx[NUM_SSI_DATA];
uint32_t ui32Index;
uint32_t count;

//
// Set the clocking to run directly from the external crystal/oscillator.
// TODO: The SYSCTL_XTAL_ value must be changed to match the value of the
// crystal on your board.
//

//
// Set up the serial console to use for displaying messages. This is
// just for this example program and is not needed for SSI operation.
//
InitConsole();

//
// Display the setup on the console.
//
UART0QueueData("SSI ->\r\n",8);
UART0QueueData(" Mode: SPI\r\n",13);
UART0QueueData(" Data: 8-bit\r\n",15);

//
// The SSI0 peripheral must be enabled for use.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);

//
// For this example SSI0 is used with PortA[5:2]. The actual port and pins
// used may be different on your part, consult the data sheet for more
// information. GPIO port A needs to be enabled so these pins can be used.
// TODO: change this to whichever GPIO port you are using.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

//
// Configure the pin muxing for SSI0 functions on port A2, A3, A4, and A5.
// This step is not necessary if your part does not support pin muxing.
// TODO: change this to select the port/pin you are using.
//
ROM_GPIOPinConfigure(GPIO_PA2_SSI0CLK);
ROM_GPIOPinConfigure(GPIO_PA3_SSI0FSS);
ROM_GPIOPinConfigure(GPIO_PA4_SSI0RX);
ROM_GPIOPinConfigure(GPIO_PA5_SSI0TX);
//ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3);
//ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);

//
// Configure the GPIO settings for the SSI pins. This function also gives
// control of these pins to the SSI hardware. Consult the data sheet to
// see which functions are allocated per pin.
// The pins are assigned as follows:
// PA5 - SSI0Tx
// PA4 - SSI0Rx
// PA3 - SSI0Fss
// PA2 - SSI0CLK
// TODO: change this to select the port/pin you are using.
//
ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 |
GPIO_PIN_2);

//
// Configure and enable the SSI port for SPI master mode. Use SSI0,
// system clock supply, idle clock level low and active low clock in
// freescale SPI mode, master mode, 1MHz SSI frequency, and 8-bit data.
// For SPI mode, you can set the polarity of the SSI clock when the SSI
// unit is idle. You can also configure what clock edge you want to
// capture data on. Please reference the datasheet for more information on
// the different SPI modes.
//
ROM_SSIConfigSetExpClk(SSI0_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 1000000, 8);

//
// Enable the SSI0 module.
//
ROM_SSIEnable(SSI0_BASE);

//
// Read any residual data from the SSI port. This makes sure the receive
// FIFOs are empty, so we don't read any unwanted junk. This is done here
// because the SPI SSI mode is full-duplex, which allows you to send and
// receive at the same time. The SSIDataGetNonBlocking function returns
// "true" when data was returned, and "false" when no data was returned.
// The "non-blocking" function checks if there is any data in the receive
// FIFO and does not "hang" if there isn't.
//
while(ROM_SSIDataGetNonBlocking(SSI0_BASE, &pui32DataRx[0]))
{
}

//
// Initialize the data to send.
//
pui32DataTx[0] = 's';
pui32DataTx[1] = 'p';
pui32DataTx[2] = 'i';

//
// Display indication that the SSI is transmitting data.
//
UART0QueueData("Sent:\r\n ",9);

//
// Send 3 bytes of data.
//
//ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0);
for(ui32Index = 0; ui32Index < NUM_SSI_DATA; ui32Index++)
{
//
// Display the data that SSI is transferring.
//
//vts_itoa(pui32DataTx[ui32Index], debugstr);
//vts_strcat(debugstr,"\r\n");
//UART0QueueData(debugstr, vts_strlen(debugstr));

//
// Send the data using the "blocking" put function. This function
// will wait until there is room in the send FIFO before returning.
// This allows you to assure that all the data you send makes it into
// the send FIFO.
//
ROM_SSIDataPut(SSI0_BASE, pui32DataTx[ui32Index]);
}
//ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);

//
// Wait until SSI0 is done transferring all the data in the transmit FIFO.
//
while(ROM_SSIBusy(SSI0_BASE))
{
}

//
// Display indication that the SSI is receiving data.
//
UART0QueueData("\nReceived:\r\n",12);

//
// Receive 3 bytes of data.
//
for(ui32Index = 0; ui32Index < NUM_SSI_DATA; ui32Index++)
{
//
// Receive the data using the "blocking" Get function. This function
// will wait until there is data in the receive FIFO before returning.
//
ROM_SSIDataGet(SSI0_BASE, &pui32DataRx[ui32Index]);

//
// Since we are using 8-bit data, mask off the MSB.
//
pui32DataRx[ui32Index] &= 0x00FF;

//
// Display the data that SSI0 received.
//
vts_itoa(pui32DataRx[ui32Index], debugstr);
vts_strcat(debugstr,"\r\n");
UART0QueueData(debugstr, vts_strlen(debugstr));
}

//
// Return no errors
//
return(0);
}

Hi Srninivas,

     

Srinivas Nagathihalli said:

I do not see the chip select, the SSI0FSS, pin going low

     Maybe, because you did not set PA3 as SSI0FSS properly. See, below. You are missing "GPIO_PIN_3" at GPIOPinTypeSSI().

     ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_2);

     Should be as below.

     ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2);

-kel

Hi Kel,

  Sorry I posted the wrong code. Since I didn't see FSS going low, I tried to manually make it low when transmitting by configuring it has output. 

I have tried with configuring PA3 as pin type SSI and it did not help.

best regards,

Srini

Srini,

So running the code you have with PA3 configured as a SSI pin, You are not seeing the FSS pin go low and you are now seeing the CLK pin toggle? Are you seeing the data pin toggle(PA4)? 

I did notice you have PA4 as RX, it is actually TX in legacy SSI mode aka not bi or quad mode.

Sheldon

Hi Sheldon,

  I do not have a CRO to look at signals. I sent did a very long tx and noticed that FSS does go low (using a multimeter. ). The clk also seems to be generated but the RX pin is always high. 

I pulled up all the pins high by configuring the GPIO pull up and now I see 0xFF received instead of 00s.

best regards,

Srinivas.

Srinivas, 

I think I maybe looking at a different schematic then the one you are talking about. Are you using a DK-TM4C129X or DK-TM4C123G. And it sounds like you are looping the TX to RX? Correct?

Sheldon

Hi Sheldon,

  I am using DK-TM4C123G development kit.

I my (custom) board, I have connected the SSI0 pins to an SPI falsh and I am unable to communicate with the flash. I will have a closer look at the timing requirements of the flash chip and the SSI signal timings.

Best regards,

Srini

Srini

When using the DK-TM4C123G are you connecting SSI RX to TX? 

Sheldon

Hi Sheldon,

  I got Tiva processor working with my flash which has a SPI interface. I had to assert and deassert  the chip select (SSI0FSS) configuring it as an output instead of depending on the SSI module to do it. I think there are some timing issues when SSI module asserts and de asserts chip select.

@Srinivas

The Custom Board is the one which connects to the DK-TM4C123G and has the SPI Flash on it. Is that correct?

What is the routing of the SPI pins on the custom board?

Amit

Hi Amit,

  My custom board is complete in itself with the tiva processor and spi flash and does not connect to the development kit. The following are the connections

SSI0FSS ->  /CS (Chip select)

SSI0Tx    -> DI  (input)

SSI0Rx     ->  DO  (output)

SSI0CLK  -> CLK

I could able to communicate with flash only if configured SSIOFSS as digital output and assert it before transmitting and deasserting after the transmission is complete.

I checked the data sheet of both tiva processor and the spi flash, the timings seem to match but it still doesn't  work. 

Best regards,

Srinivas.

@Srinivas,

Which SPI Flash part is. A lot of material on the web mention that routing of the signals for SPI Flash is tricky. Also can you send the schematic of the board between the SPI Flash and the TIVA along with the PCB routing details, on trace lengths, trace length match, track layout.

That would be useful to determine if the timing is optimal for your PCB

Amit

@Srinivas 

I have the same board as you and the same problem you describe.  Did you ever find the solution for this?  It would be greatly appreciated.

Brandon

Hi Brandon,

  I have configured the chip select pin SSI0FSS as an output and not as SSI0FSS. 

The configuration is as follows

ROM_GPIOPinConfigure(GPIO_PA2_SSI0CLK);
//ROM_GPIOPinConfigure(GPIO_PA3_SSI0FSS);
/* Default functioning of SSI0FSS doesn't seem to work with flash.
* Toggle PA3 to assert and deassert CS for flash */
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3);
ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3 , GPIO_PIN_3);
ROM_GPIOPinConfigure(GPIO_PA4_SSI0RX);
ROM_GPIOPinConfigure(GPIO_PA5_SSI0TX);

ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_2);

Whenever I need to transfer data I drive that output LOW and then drive it HIGH once the transfer is complete.Also experiment with having some delay after driving the FSS LOW and the actual initiation of the transfer(in my case I put some delay between making FSS LOW and initiating the DMA transfer)

Kind regards,

Srinivas.

Is there an SPI example for the TM4C1294XL launchpad?

Where is this spi_master.c file? I only see uart, can and enet examples..

Thanks,

Stephen

Stephen Keng said:

Where is this spi_master.c file?

"\\examples\peripherals\ssi"

- kel

Hello Stephen

Please be aware the example as Kel mentioned is for TM4C123. There is an application note on differences between TM4C123 and TM4C129 (hw and sw) that would be useful in migrating the examples

Regards

Amit

From 123 to 129

SysCtlClockSet change to SysCtlClockFreqSet

GPIO_PA4_SSI0TX change to GPIO_PA4_SSI0XDAT0

Compile issue.

**** Build of configuration Debug for project SPItest ****

"c:\\ti\\ccsv6\\utils\\bin\\gmake" -k all
'Building target: SPItest.out'
'Invoking: ARM Linker'
"c:/ti/ccsv6/tools/compiler/arm_5.1.8/bin/armcl" -mv7M4 --code_state=16 --float_support=FPv4SPD16 --abi=eabi -me -O2 -g --gcc --define=ccs="ccs" --define=PART_TM4C1294NCPDT --diag_warning=225 --display_error_number --diag_wrap=off --gen_func_subsections=on --ual -z --stack_size=256 -m"blinky_ccs.map" --heap_size=0 -i"c:/ti/ccsv6/tools/compiler/arm_5.1.8/lib" -i"c:/ti/ccsv6/tools/compiler/arm_5.1.8/include" --reread_libs --warn_sections --display_error_number --diag_wrap=off --xml_link_info="SPItest_linkInfo.xml" --rom_model -o "SPItest.out" "./spi_master.obj" "./startup_ccs.obj" "../blinky_ccs.cmd" -l"libc.a" -l"C:/ti/TivaWare_C_Series-2.1.0.12573/examples/boards/ek-tm4c1294xl/blinky/ccs/../../../../../driverlib/ccs/Debug/driverlib.lib"
<Linking>

undefined first referenced
symbol in file
--------- ----------------
UARTStdioConfig ./spi_master.obj
UARTprintf ./spi_master.obj

error #10234-D: unresolved symbols remain
error #10010: errors encountered during linking; "SPItest.out" not built

>> Compilation failure
gmake: *** [SPItest.out] Error 1
gmake: Target `all' not remade because of errors.

**** Build Finished ****

I already linked driverlib.lib... Don't think I left anything out.

EDIT: The issue is resolved here. http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/249645.aspx

Hello Stephen

The UART Configuration files come from the uartstdio.c which is not a part of the driverlib.lib You would need to copy/link the files into your project

Regards

Amit

Hello Amit

I want to configure the FSS (chip select pin ) for my oled for tm4c1233h6pz .

I am using SSI0 mode for my oled(SSD 1306) interface to tm4c1233h6pz.

In the pinmap.h file from TI, for SSI0

GPIO_PA2_SSI0CLK ( clock select)
GPIO_PA3_SSI0FSS (chip select)
GPIO_PA5_SSI0TX ( MOSI ) is used.

But I want to configure PA6 for SSI0FSS . how can i do this.

I am making FSS as high to low for DATA transfer and after data transfer FSS should become high again.

Please suggest me the procedure to configure my FSS for PA6 for my application.

Thank you

Hello Nethra

Please do not post in multiple places. Makes it difficult for tracking. (DO NOT REPLY TO THIS THREAD, WE WILL USE THE OTHER THREAD OPENED BY YOU)

Regards
Amit