Need to confirm SDRAM compatibility?

Your linking to datasheet - that SRAM - may save substantial, "wear/tear" upon each/every of your (potential) hapless helpers...

Fair enough...

 Download PDF

Datasheet reveals part to be 64Mb - not 64MB.  (that - first aroused my curiosity) 

Pgs: 8-10 illustrate 4, 8 & 16 bit data-bus attachments.  I'm uncertain if you can realize 16 bits - @ full speed - w/MCUs here.  Address requirements/match determination should be not too difficult for you. 

Remaining then: 2 clocks, vanilla "\CS & \WE" and RAS/CAS.  Compare/contrast first for presence of those signals (your chosen MCU) and if present - scan further to confirm that timing requirements are achievable...

Choice & verification remains your responsibility - beyond my pay-grade (and desire) to welcome that role...  Believe the "tools" needed for your analysis have been herein guide-posted...

The TM4C129 has been tested with MT48LC3216A2TG, which can go upto 143MHz. However what is important to note is that the TM4C129 SDRAM interface will work at no more than 60Mhz. Hnece you will not be able to realize the full throughput of the chose part anyways.

Micah Lawrence said:

Micron: MT48LC4M16A2P-7E IT

 Hi Selected part appear to be a PC133 part so a clock cycle of 133MHz match internal 60MHZ operation of EPI, again also slowest 75 part can match timing but all depend of how you connect dram to EPI and how you intend access data from (single R/W or burst) and if no other peripheral is EPI connected to. May be necessary add some GLUE logic  to manage signals and timings.

Micah Lawrence said:

 TM4C1290NCPDT

 This part is currently preview and not available, no public plan fof GA so ask your FAE or try sampling the alternate part suggested from  parent TM4C129DNCPDT available in limited sampling as XM4C129DNCPDT and near it final GA release date.

Thanks for the replies everyone.  I realize the SDRAM I linked to can be physically wired up to the EPI module (all connections are there, as required), but I didn't now whether the SDRAM protocol, and other specifics (such as the init sequence) are properly duplicated by the EPI module. How do you verify compatibility of the actually controller (not the electrical aspect).  Is brute force comparison of state machines and timing diagrams the only way, or is there a device-support list somewhere?

Micah

The EPI modules does this very well based on testing that has been done. What you need to take care is the timing parameters are programmed correctly in EPI, so that EPI knows when to time the signalling for SDRAM to work correctly. Unfortunately there is no device support list for vendors supplying SDRAM parts.

But we can help you getting the interface up with programming sequence sharing.

Amit

@ Amit,

Thanks your focused detail re: EPI and SDRAM - our group has found your writings helpful.  Might you post that "129x" programming sequence you reference right here - for the benefit of many?  (private exchanges surely cause added, "wear/tear" upon you/vendor staff - and force extra effort upon each/every of your motivated/interested potential users. 

And:

Amit Ashara said:

Unfortunately there is no device support list for vendors supplying SDRAM parts.

One hopes that this announcement is, "time-based" - rather than "policy based."  Having some substantial, past success w/in tech sales, (co-founded, took tech firm public)  I can report that client, "comfort & convenience" is most welcome - and quickly/efficiently translates to your bottom line.  "Device support list" saves much client "time/effort"  and proves critically important in steering clients around/away from dreaded, "dead-end."   This extra effort keenly accelerates the volume purchases of your devices - clearly yielding a, "win-win!" 

For folks who would be interested in using SDRAM Mode on TM4C129 devices. The following is a sequence of working example of an external SDRAM (MT48LC3216A2TG) with System Clock of 120MHz and SDRAM Max Clock of 60MHz. The Equations to compute the refresh time is self-explanatory.

What is not given here is that the Pin Configuration for using EPI needs to be done by the user.

  //
  // Enable the Clock to EPI
  //
  SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
  //
  // The Max External Clock Rate Supported is 60MHz. Hence based on the System Frequency
  // configure the divider. A value of 0 means external clock = System Clock
  // The System Clock for this example is 120MHz.
  //
  EPIDividerSet(EPI0_BASE, 1);
  //
  // Set SDRAM Mode for EPI
  //
  EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);
  //
  // Program the Refresh Counter Value and EPI Core Clock for loading proper timing parameters
  //                    64ms           8192             1/Clock
  // Value of RFSH = (tRefresh_us / number_rows) / ext_clock_period
  // The Core Frequency is same as the External Clock Frequency which in this case is 60MHz.
  //
  EPIConfigSDRAMSet(EPI0_BASE, EPI_SDRAM_CORE_FREQ_50_100 | EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT, 468);
  //
  // Configure the Address Aperture and Base Address for the CPU to access the SDRAM Memory
  //
  EPIAddressMapSet(EPI0_BASE, EPI_ADDR_CODE_SIZE_16MB | EPI_ADDR_CODE_BASE_1);
  //
  // Wait for Init to Be Completed
  //
  while((HWREG(EPI0_BASE+ EPI_O_STAT) & 0x00000040) != 0x00000040);

We can add support lists going forward but this would not be any instant soon...

Amit

Thank you for letting us know that the MT48LC3216A2TG is supported by the TIVA 129.   Is there an obtainable chip that you can suggest?   I can only find one web page regarding this chip that I can understand, and it doesn't take me to the kind of site I'd leave my credit card information on.

Is there a chip provided by Digikey or Mouser that is supported?

Hello Robert,

MT48LC32M16A2TG is also tested and is available on DigiKey.

Regards

Amit

Thank you Amit, you are awesome!

I have been trying with the MT48LC32M16A2 attached to XM4C129AENCPDT, but nothing meaningful comes out of the test write/read. Does anyone have a sample code to look into in addition to lines in the above posts? All GPIO configurations has been carefully checked etc..

 Hi Peter, try this board, all example and source code are available from link. It cost few US$ more than DK kit but is more and more equipped and also SDRAM is on board to support full color graphics on LCD.

Thank you, I willl look into this option.

A complete functional project is attached here for the TM4C129ENCPDT to MT48LC32M16A2 interface. It was a mysterious hardware fault in the prototype board, we simply build a new board.

For what it's worth, I'm the original poster of this question so I thought I'd post an update.  We originally used a compatible device with CL=2, and it worked as expected since CL of TM4C matched CL of SDRAM.  However, that device went EOL, and we've since tested with the suggested replacement (MT48LC4M16A2P-6A) which is a faster part, but has CL=3.  It did work in our application (passed our SDRAM tests), but the standard disclaimer applies--individual results may vary. :)

Thank you very much for your support.

Marco Crivellari