Jitter spec for EMIF CLK for the TMS570LS3137

dwane bell

Hello:

I need the Jitter specs of the EMIF_CLK. I'm working on a design with a customer and they plan on using the EMIF_CLK to clock their FPGA and we need the jitter tolerance in order to perform timing analysis. This parameter is not listed in the data sheet. Can someone please provide this data. Thanks.

over 11 years ago

0 Praveen Kumar Ravichandran over 11 years ago

TI__Expert 4610 points

Hi Dwane,

I have forwarded your query to one of our experts. They will get back to you. Due to the year-end holidays and vacations , please expect delay in the responses.

Regards,

Praveen

0 Zhaohong Zhang over 11 years ago in reply to Praveen Kumar Ravichandran

TI__Mastermind 22715 points

Dwane,

The EMIF_CLK is divided down from HCLK (normally PLL). It shares the same characteristics from PLL (divided down).

Thanks and regards,

Zhaohong

0 dwane bell over 11 years ago in reply to Zhaohong Zhang

TI__Expert 3240 points

Zhaohong:

Your post did not answer my question. What are the jitter specs for the clock?

0 Sunil Oak over 11 years ago in reply to dwane bell

TI__Mastermind 49120 points

Dwane,

The PLL can add jitter of up to 5% to the clock period. This is completely random jitter (hence averages to zero). This is also why it is not a datasheet parameter.

PLL1 on LS3137 MCU can also be used to intentionally modulate the PLL's output clock. This is not factored into the 5% random jitter figure.

Regards, Sunil

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Jitter spec for EMIF CLK for the TMS570LS3137