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TMS570LS3137 - Linker Generated ECC

Charles Johnston
Expert 2690 points
Other Parts Discussed in Thread: HALCOGEN

Hello,

Version 5.1.2 of the ARM Compiler Tools includes a new option for Linker Generated ECC.  The readme.txt has a brief description.  Part of the command file change includes device specific parameters.

1) Where can I find these parameters for the TMS570LS3137ZWT?

2) Will this be added to the next version of HALCoGen?  If so, when is the next version due?

Thanks, Charlie Johnston

  • 0
    TI__Genius 9015 points

    Here is an example for the LS3137 (Note: The palign(32) in the SECTIONS section is a temporary fix for an issue in the ECC generated by the linker):

    /* Linker Settings                                                            */

    --retain="*(.intvecs)"

    -stack=0x1000

    /*----------------------------------------------------------------------------*/

    /* Memory Map                                                                 */

    MEMORY{

        VECTORS (X)  : org = 0x00000000 len = 0x00000020 vfill = 0xffffffff

        FLASH0  (RX) : org = 0x00000020 len = 0x0017FFE0 vfill = 0xffffffff

        FLASH1  (RX) : org = 0x00180000 len = 0x00180000 vfill = 0xffffffff

        VECTORS_ECC  : org = 0xf0400000  len = 0x00000004 

                       ecc = { input_range = VECTORS, algorithm   = eccalgo,

                               fill        = true }

        FLASH0_ECC   : org = 0xf0400004  len = 0x0002FFFC

                       ecc = { input_range = FLASH0, algorithm   = eccalgo,

                               fill        = true }

        FLASH1_ECC   : org = 0xf0430000  len = 0x00030000

                       ecc = { input_range = FLASH1, algorithm   = eccalgo,

                               fill        = true }

        STACKS  (RW) : origin=0x08000000 length=0x00001300

        RAM     (RW) : origin=0x08001300 length=0x0003ED00

    }

     ECC

    {

       eccalgo : address_mask = 0x003ffff8

                 hamming_mask = R4

                 parity_mask  = 0x0C

                 mirroring    = F021

    }

    /*----------------------------------------------------------------------------*/

    /* Section Configuration                                                      */

    SECTIONS{

        .intvecs : palign(32) {} > VECTORS

        .text    : palign(32){} > FLASH0 | FLASH1

        .const   : palign(32){} > FLASH0 | FLASH1

        .cinit   : palign(32){} > FLASH0 | FLASH1

        .pinit   : palign(32){} > FLASH0 | FLASH1

        .bss     : {} > RAM

        .data    : {} > RAM

        .stack   : {} > STACKS

    }

    /*----------------------------------------------------------------------------*/

     

     As to the HALCoGen question, I have forwarded that to one of the HALCoGen experts to answer that.

  • 0 in reply to John Hall
    Expert 2690 points

    Hi John,

    Correct me if I'm wrong, but won't  

    .intvecs : palign(32) {} > VECTORS

    force FLASH0 to start at 0x00000100, not 0x00000020 as desired in the MEMORY section?

    Thanks, Charlie

  • 0 in reply to John Hall
    Expert 2690 points

    Hi John,

    Also - should the input range for FLASH0_ECC and FLASH1_ECC be set to VECTORS?

    Thanks, Charlie

  • 0 in reply to Charles Johnston
    TI__Genius 9015 points

    Hi Charles,

    palign(32) means to align on 32 (0x20) byte boundaries

    On the input range question.  Copy and paste error on my part.  I have gone back and corrected my original post.

  • 0 in reply to John Hall
    Expert 2690 points

    Hi John,

    One more question. 

    Can the memory definitions for the flash be combined or do they have to be kept as FLASH0 and FLASH1?

    Thanks, Charlie

  • 0 in reply to Charles Johnston
    TI__Genius 9015 points

    Hi Charlie,

    They can be combined.  Our generic linker files just put each bank into it's own section.

  • 0 in reply to John Hall
    Expert 2690 points

    4035.sys_link.cmd.txt

    Hi John,

    Attached is my sys_link.cmd file.  The output is generated, but CCSv5 won't load it.  I get the error:

    CortexR4: Loader: One or more sections of your program falls into a memory region that is not writable.  
  These regions will not actually be written to the target.  Check your linker configuration and/or memory map.
CortexR4: File Loader: Data verification failed at address 0xF04042F4 Please verify target memory and memory map.
CortexR4: Unable to terminate memory download: (Error -1003 @ 0x2BC5) Internal error: Invalid parameter passed to function. 
  Restart the application. If error persists, please report the error. (Emulation package 5.1.207.0) 
CortexR4: GEL: File: C:\star\1425_PCU\Prototype\SW-Op\SystemController\Debug\Proto_SW-Op_SC.out: a data verification error occurred, file load failed.

    This error pops up as soon as the .ecc sections attempt to load.

    Do you know what the problem might be, or should I post this on the Code Composer Forum?

    Thanks, Charlie

     

     

  • 0 in reply to Charles Johnston
    TI__Genius 9015 points

    Charles,

    What version of CCS are you using?

    What is the version for Hercules emulation that is installed (for CCS v5.5 most current version is v5.5.1)?

    The can be found in Help->About Code Composer Studio->Installation Details.

  • 0 in reply to John Hall
    Expert 2690 points

    Hi John,

    We're using CCS v5.4.0.00091, and Hercules Emulation v5.4.0.4.

    Thanks, Charlie

  • 0 in reply to Charles Johnston
    TI__Genius 9015 points

    Hi Charlies,

    There are issues with 5.4 and Hercules Emulation v5.4.0.x with respects to ECC usage.  This is corrected in CCS v5.5 and Hercules Emulation v5.5.1.

  • 0 in reply to John Hall
    Expert 2690 points

    Hi John,

    I'll have to get back to you later on this.  Our company policies require IT authorization for upgrades.

    Do you know when CCSv5.6 will be released?  I assume this change plus the compiler v5.1.2 or above would be in that package.  That would be the easiest way to get all project members on the same CCS platform.

    (I can ask this last question on the CCS forum, but they are not as responsive as your group.)

    Thanks, Charlie

  • 0 in reply to Charles Johnston
    TI__Genius 9015 points

    Hi Charlie,

    The next version of CCS will be v6.0.  Last I saw on their schedule it looked like it would come out end of 1st quarter, beginning of 2nd quarter.

  • 0 in reply to John Hall
    Expert 2690 points

    Thanks, John

    I'll look into the latest emulator via the built in CCS "software updates".

    Thanks, Charlie

  • 0 in reply to Charles Johnston
    TI__Genius 9015 points

    Charlie,

    The Emulation update needed unfortunately only works with CCS v5.5.