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RM48L952 EMIF read and write

Other Parts Discussed in Thread: HALCOGEN, RM48L952

VCLK3 is 100MHz,

sdram init code is:

-------------------------------------

void emif_SDRAMInit(void)
{
/* USER CODE BEGIN (0) */
/* USER CODE END */

uint32 buffer;

uint32 waitj = 1000;

/*timing*/
emifREG->SDTIMR = (6U << 27U)| //RFC
(1U << 24U)| //RP
(0U << 23U)| //Rsvd
(1U << 20U)| //RCD
(0U << 19U)| //Rsvd
(1U << 16U)| //WR
(4U << 12U)| //RAS
(6U << 8U)| //RC
(0U << 7U)| //Rsvd
(1U << 4U)| //RRD
(0U << 3U); //Rsvd

/* configure refresh rate*/
emifREG->SDSRETR = (uint32)6U;

emifREG->SDRCR = 1562U; //RR value

/** -general clearing of register
* -for NM for setting 16 bit data bus
* -cas latency
* -BIT11_9CLOCK to allow the cl field to be written
* -selecting the banks
* -setting the pagesize
*/

emifREG->SDCR = (0U << 31U)| //SR
(1U << 14U)| //NM ,16-bit sdram
(3U << 9U)| //CL
(1U << 8U)| //bit11-9 lock
(2U << 4U)| //IBANK
(elements_256); //pagesize


while(waitj--);

/* USER CODE BEGIN (1) */
/* USER CODE END */
}

__________________

PINMUX config in halcogen is:

--------------------------------------------------------------------------------------------------------------------------------------

with code and config abovem,sdram read and write can be work well in RM48L950HDK ,but can't in RM48L950HDK,

please give help,thanks.

  • Hello Ron,

    I have forwarded your question to one of our experts and they should respond soon.

  • Ron,

    The max freq. for the EMIF on RM48L95x is only 50MHz; unfortunately.   (this was obviously a 'miss').

     

    Sorry about this.  It probably will work or almost work under nominal conditions near 80-100MHz but if you change parts or change conditions it could fail;   we can't spec it reliably above 50MHz.   Especially if your silicon revisions are differnet on your two parts, we tweeked the timing a bit trying to correct the problem between rev A, B but weren't able to make it work.

    So, the first thing I'd try is to slow down the clock from 100 MHz to 50MHz.

    -Anthony

  • thanks for your remind.

    we try this:

    we modify VCLK3 to 40MHz,

    modify configuration timing using halcogen like below:

    so the sdram init function is:

    void emif_SDRAMInit(void)

      uint32 buffer;

       emifREG->SDTIMR  = (7U << 27U)|
                          (1U << 24U)|
                          (0U << 23U)|
                          (1U << 20U)|
                          (0U << 19U)|
                          (1U << 16U)|
                          (3U << 12U)|
                          (3U << 8U)|
                          (0U << 7U)|
                          (1U << 4U)|
                          (0U << 3U);

     /* configure refresh rate*/
       emifREG->SDSRETR = (uint32)7U; 
       emifREG->SDRCR   = 1000U; 

    /**  -general clearing of register
    *    -for NM for setting 16 bit data bus
    *    -cas latency
    *    -BIT11_9CLOCK to allow the cl field to be written
    *    -selecting the banks
    *    -setting the pagesize
    */  
        emifREG->SDCR    = (0U << 31U)|                                
                          (1U << 14U)|                                
                          (3U << 9U)|   
                          (1U << 8U)|                                 
                          (2U << 4U)|               
                          (elements_256);          
    /* wait for a read to happen*/
       buffer             = *PTR;
       buffer             = buffer;

    emifREG->SDRCR   = 1000U;

    }

    7178.IS42S16400F-7BL.pdf

    we use TI's RM48L952 HDK ,sdram chip is IS42S16400F-7BL

    I have insert  datasheet of IS42S16400F-7BL.

    please give some help,thanks

     

  • Hi Ron,

    What exactly are you seeing as a symptom of the problem?

    Also in your original post you mentioned "with code and config abovem,sdram read and write can be work well in RM48L950HDK ,but can't in RM48L950HDK"  but both of these are the same.  I didn't understand this so please elaborate as it might be a good clue.

    Did you check the SDRAM_OFF jumper on the HDK as a possible source of problem?  It's near the SDRAM chip and is a 2 pin jumper.