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SDRAM and TM4C129DNCPDT

Other Parts Discussed in Thread: TM4C129DNCPDT

Hi, i'm with a problem in my project with RAM memory. 

Then I will explain:

I'm finish a power quality device in my P.h.D, and this device work with 2 processors, one FOGA ( Signal Processing) and ARM (TIVA ) work with manager of system. In my case ARM run GPS/ BLUETOOTH/ RTC (TXCO) AND SDCARD. The communication between FPGA and ARM is executed by SPI bus. 

In my prototipe I'm using Stellaris Launchpad, but my problem happen when I need open a new file on SD. During this time ( 2 seconds) I cant buffer(2Mbytes ) that arrive of FPGA. After search about dual port FIFO and other chip to solve this problem, I found TM4C129DNCPDT that can work with external SDRAM/SRAM memory. I would like to receive suggestion about what SDRAM chip that I can put in my board and I will open my files Gerber and software about work this . 

Anyone can help me choise a good chip that can work in this situation. 

  • Hi Carlos,

    There is a post on SDRAM and TM4C129 which you can refer to. This had some good details from the forum members and code example which is working on TM4C129

    http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/309853.aspx

    Amit

  • Thanks. Do you have or TI have some reference designer with TIVA and SDRAM.

  • Hi Carlos,

    In the datasheet for TM4C129 there is a table for connection of the SDRAM signals to the EPI Pins. You may want to refer to the System Design Guidelines for PCB layout considerations.

    We hope to have an app note sometime later.

    Regards

  • Hi Carlos,

        You, can also look into how DK-LM3S9B96 interfaces with the SDRAM expansion board. But, that is not TIVA.

    -kel

  • Hi, friends after search on internet details about SDRAM/SRAM on TIVA, a found some important details, I will post all my search in this forum, to provide suport to new designer . 

    Then after verify a Big datasheet of TIVA ( link below ) I found  the follow informations 

    Datasheet : http://www.ti.com/lit/ds/symlink/tm4c129dncpdt.pdf 

    Verify page:837 in this page have schematic ( Diagram block ) of EPI Example Schematic for Muxed Host-Bus 16 Mode . Then I believe that this schematic can be used to build my application, but in my case I will use only SRAM. The SRAM of schematic is CY62147EV30LL-45ZSXI (http://www.digikey.com/product-detail/en/CY62147EV30LL-45ZSXI/428-2073-ND/1205253) and this memory is a low cost memory . 

    I would like to receive suggestion and confirmation with this hardware is right in 3 days I will post complete schematic with final circuit. 
    Thanks for atention and best regards 

  • @ Carlos,

    While you're making good progress - please do not let, "low cost" over-shadow other, important issues. 

    Often memory devices which are, "low cost" suffer slow access times & are unlikely to be, "best-brightest."  It is your responsibility to comb thru data sheets (both your MCU in this external memory's "timing" regard) and multiple, candidate memory devices - to insure, "safety margins" exist over lot, temperature & operating voltage.  (memory vendors' sites likely further detail...) 

    Perhaps better to initially, "over-specify" a device (to insure it will work) and then later see if the spec can be, "relaxed," via employ of a, "lower cost" device...

  • @Cb1_mobile, 

    Thanks for you attention and your comments, I agree with you, I  can use keywords, that didnt represent all applications. 

    In my case I will develop hardware and firmware, with memory of datasheet and TIVA. I want share my experience and I would like that forum help me avoid problems in my project. 

    Thanks for attention. 

  • @ Carlos/interested others,

    Our group is reasonably active here - use multiple of this vendor's MCUs/otherdevices - but believe that multiple sources often enrich & extend tech awareness, knowledge, application & mastery.  While it's most always best to, "stick with" components/circuits employed in reference designs and/or focused Ap Notes - similar designs from other sources often prove revealing & beneficial.

    There are multiple ways/means to, "skin your design cat."  Hunting w/in one small corridor - w/in a very broad silicon forest - may not always harvest best/biggest, most appropriate "game."

    btw: detail, imagination, roadmap - postings provided seem to (at minimum) "approach" the value of "single sentence link/Verify" earlier awarded.    Multiple Verifies may be clicked/awarded...