What is the value of SIDE field during Unimpelmented Peripheral Region Access ABORT?

Pashan,

Not an expert on the core - so just going by the Cortex R4 TRM (ARM document).  If you want to double check the TRM, you probably need to post on ARM's forum.

It says in the description for the Auxiliary fault status registers:  "The contents of an auxiliary fault status register are only valid when the corresponding Data or Instruction Fault Status Register indicates that a parity error has occurred. At other times the contents of the auxiliary fault status registers are Unpredictable."

Since the ABORT generated by accessing unimplemented peripheral frames isn't a parity or ECC error, I'd say the SIDE field is Unpredictable in this case.

Best Regards,

Anthony

Hi Pashan,

If I look at the ARM documentation (DDI0363G), then I would expect that a fault in a peripheral frame data access would have a side value of 00b, as the access would be over the AXI master interface.  If this is not what you are seeing, then we should probably contact ARM for clarification.

Regards,

Karl

Hello Karl,

I am seeing BTCM instead of AXI when I perform CRC Frame Address IMPRECISE ABORT.
Please help me understand with the ARM Core related expected result.
May be someone at TI can create a DEMO Project and verify if CRC Frame Address UNIMPLEMENTED IMPREECISE ABORT occurs with AXI instead of BTCM as SIDE Field value.

Thank you.
Regards
Pashan

Hello Pashan,

As this is an ARM issue, we will likely push to ARM if extensive debug is needed.  

Can you please confirm that the DFSR is indicating a parity or ECC error?  As stated as a usage constraint of ADFSR, without this in the DFSR the ADFSR contents are unpredictable (see DDI0363G, P. 4-50)

Regards,

Karl

Hello Karl,

Sorry for the confusion. It is not a Parity or ECC Error Abort. It is IMPRECISE EXTERNAL ABORT.

Can you please tell me how to generate Imprecise Parity/ECC Error?

Thank you.
Regards
Pashan