I'm having problems getting the EMAC Ethernet peripheral to work. I'm using a DK-TM4C129X board with unqualified XM4Cxxx part on it. I'm using the internal PHY.
I think I found an error in the Data Sheet and I have made some progress.
It appears that the following statement on page 1608 of "Tiva TM4C129XNCZAD Microcontroller Data Sheet" is not true.
Quote from Data Sheet:
TBS1: Transmit Buffer 1 Size
These bits indicate the First Data Buffer byte size. If this field is 0, the DMA ignores this buffer and uses Buffer
2 or next descriptor depending on the value of TCH (Bit 24).
End Quote.
I cannot make that work at all. I just get FBI errors (fatal bus error) and AE field is 3 (Error during TX DMA Read Data access). This is when I make buffer 1 size 0 to try to use only 2nd buffer. I suspect the same is true of RX descriptors.
I tried using just buffer 1 with buffer 2 size 0. I also tried using chained TX descriptors. In both cases I don't get FBI errors any more. The transmit DMA seems to be working - sort of. It activates interrupts at completion and moves the hw TX DMA descriptor pointer as expected. There appears to be no output from the PHY so I cannot see any packets on the wire. I have not tested if the TX DMA engine wraps at the end of the TX descriptor list.
The TCP/IP stack that I use breaks a transmit packet up into 2 or 3 or more non-contiguous buffers. The first buffer has 14 bytes in it (size of ethernet header, I think). The remaining buffer(s) have the rest of the packet. I create TX descriptors to match these buffers.
The receiver DMA can receive packets okay. It signals interrupts on completion and I can retrieve the packets and I can give ownership of descriptor back to DMA. But it has a major problem. It will not wrap back to the base of the RX descriptor ring. I have tried using chained descriptors and using the RER bit in the final descriptor (and also tried with both together) but it just won't wrap back even when it owns the descriptors at the start of the ring. To debug, I read EMAC_HOSRXDESC register and it shows that the DMA did not wrap to RX descriptor base.
When the RX DMA reaches the end of the descriptor list, it is still running and continues to give interrupts that say RX overflow every time a packet is received. Of course it doesn't actually receive the packet because it does not have a place for it because it did not wrap back to the start of the descriptors.
I'm using my own routines to manage the EMAC and the GCC tool-chain for building. I'm using only "normal" DMA descriptors and both descriptors and buffers are in SRAM. Both RX and TX buffers in the descriptors (only using buffer 1 in each descriptor) is 128 bytes in size.
I notice that all the examples use the enhanced/extended DMA descriptors instead of the normal descriptors. I don't know if that is the cause of my problems. I notice also that the FS, LS, and other DMA control bits move around in the descriptors based on using normal or extended descriptors. That seems odd to me.
Thanks for any help you can provide.
