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n2het - parity check doesn't work

Pablo Cottens
Genius 3020 points
Other Parts Discussed in Thread: HALCOGEN, RM48L952

Hello,

I'm running a parity check for the n2het, but for some unknown reason, it doesn't catch a parity error during the boot process.

The bootloader was coded by me, I'm not using HALcogen. And I know that I'm initializaing both N2het modules (bit 3 and 15 in MSIENA). 

void NHET1_RAM_ParityCheck() {
	volatile unsigned int parError = 0;

	asm(" b #-8"); /*For debug purposes*/
	N2HETReg1->HETPCR = 0x10AU;
	N2HET1_RAM_PARITY_LOCATION ^= 0x1U;
	N2HETReg1->HETPCR = 0xAU;

	parError = N2HET1_RAM;

	if(!(ESMReg->ESMSR1 & 0x80U)) {
		while(1);
	} else {
		ESMReg->ESMSR1 = 0x80U;
		N2HETReg1->HETPCR = 0x10AU;
		N2HET1_RAM_PARITY_LOCATION ^= 0x1U;
		N2HETReg1->HETPCR = 0xAU;
	}
}

All other modules run the parity check without problems, but this one isn't working. Any ideas why?

  • 0
    Genius 3020 points

    No bits are being set in the ESM module. And when I check the parity RAM I notice that it's entirely made up of 0 (zeros). This makes me think that the N2het ram is not being initialized, but as I said before, they are being set accordingly.

  • 0 in reply to Pablo Cottens
    TI__Guru**** 191906 points

    Hello Pablo,

      By default the parity scheme is ODD. If you have all zeros in the data then the parity bit should be 1. Since you see 0 in the parity RAM it means the parity is not generarted per the corresponding data. You need to make sure that you enable parity checking (set the PARITY_ENA field of the HETPCR register to 0xA) before you initialize the NHET RAM. This will allow automatic parity bit generation when you perform the NHET RAM initailization.

     

  • 0 in reply to Charles Tsai
    Genius 3020 points

    As you can see I am enabling parity for NHET in my parity check function. I have just inserted 2 lines of code in my bootloader, just before the memory initialization (bits 3 and 15 of MSIENA):

    NHETReg1->HETPCR = 0xAU;

    NHETReg2->HETPCR = 0xAU;

    The result is the same as before. Maybe I didn't understand your suggestion correctly?

  • 0 in reply to Pablo Cottens
    TI__Guru**** 191906 points

    Hello Pablo,

      I created a small test to autoinitialize the NHET RAM and also do a parity test. Look at the sys_main.c. The rest of the code are generated from HalCoGen.  I'm able to see the ESM group 1 bit 7 getting set for NHET parity failure. Please take a look and see if you can reproduce it at your side.

    3348.NHET_parity_test.zip

    regards,

    Charles

  • 0 in reply to Charles Tsai
    Genius 3020 points

    It doesn't work. It sets parity_fail = 1. It doesn't set bit 7 of the ESMSR1

  • 0 in reply to Pablo Cottens
    TI__Guru**** 191906 points

    ok, this is weird. I ran on a HDK board and the parity_fail = 0 and the ESMSR1 bit 7 is set. Are you running on a HDK board or some other board? Which device do you have?

  • 0 in reply to Charles Tsai
    Genius 3020 points

    Yeah, I know it's weird. All other parity checks work accordingly, except for this one.

    I have a Hitex functional safety kit with RM48L952 microcontrollers.

  • 0 in reply to Pablo Cottens
    TI__Guru**** 191906 points

    I will need to talk to my colleagues if they have seen such behavior on a Hitex/RM48L952 board.

  • 0 in reply to Charles Tsai
    Genius 3020 points

    Ok, thank you for your help. I'll keep working on it on my side, and if I come by a solution I'll post it here.

  • 0 in reply to Pablo Cottens
    TI__Guru**** 191906 points

    Just FYI. I ran the same code that I sent you on a Hitex board and was able to see the HET parity failure with the ESMSR1 bit 7 set.

    Do you at least see all the parity bits get set to 1 after NHET memory initialization? Earlier in your problem description you said all the parity bits are 0 after memory initialization. If you single step through the code, do you see the parity bit get flipped to zero after you enter test mode to intentionally change the parity value?

     

  • 0 in reply to Charles Tsai
    Intellectual 585 points

    Hello,

    I am experiencing this same problem on TMS570. I have verified when I produce a pariy error, by setting TEST bit in HETPCR and enabling PARITY_ENA, that register register HETPAR has the NHET address with the parity error that I introduced but this error is not signaled in ESM module ESM1 bit 7.

    But I have also verified that when NHET is on, HETGCR.TO = 1, then even before I read the address with parity error, just after I change the parity bit in instruction 0 program field, the parity error is signaled to the ESM module!!

    So, why when NHET is on the error is forwarded to ESM and not when NHET is not running.

    This is very important because I would like to run the NHET parity test without running NHET!!

    Thanks for helping,

    Francis.

  • 0 in reply to Francisco Torres
    TI__Guru**** 191906 points

    Hello Francis,

      Once you enable TEST mode to program the parity bit, please make sure that you disable TEST mode before reading the RAM. I use the below sequence  and I can see the error sent to the ESM and nERROR pin is lit. The code assume ODD parity scheme. Here I'm writing to the Data field of the first instruction with 0xFF. Since it is a ODD parity scheme checking, an parity error will result if the corresponding parity bit is 0. Also the NHET here is not running. There is no program in it yet.

    hetRAM1->Instruction[0].Data = 0xFF;

    hetREG1->PCR = (1 << 8); /* enable test mode to write parity bit */

    *(&NHET1RAMPARLOC+2) = 0;

    hetREG1->PCR = (0 << 8) | 0xA; /* Disable test mode and enable parity checking */

    nhet_data = hetRAM1->Instruction[0].Data;

    regards,

    Charles

  • 0 in reply to Charles Tsai
    Intellectual 585 points

    Thanks a lot Charles!! I can confirm that this solves the problem. As far as I know this is the only mode where parity test bit needs to be disabled before reading from RAM to generate ESM error.

    Thanks!

  • 0 in reply to Francisco Torres
    TI__Guru**** 191906 points

    Hello Francis,

      Glad that you resolve the issue. Please let me know if you have further questions.

    Regards,

    Charles

  • 0 in reply to Charles Tsai
    Genius 5660 points

    Hello Charles,

    For TCRAM, within RAMCTRL register there is a bit ECC WR EN for generating ECC Error Test of TCRAM.

    Do I must disable ECC_WR_EN bit [like you did for HET RAM Parity Test] for testing TCRAM ECC Error Test?

    Or, even if ECC_WR_EN = 1 and ECC value is wrong while CPU read the respective TCRAM Cell, it will generate ECC Error condition?

    Please confirm which of the above statement is correct.

    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Guru**** 191906 points

    Hello Pashan,

      Sorry for the late reply. I missed your post until now. To answer your question, for TCRAMW there is no need to reset the ECC_WR_EN before reading the RAM location. I agree it is not very consistent between modules. Please let me know if you have further questions.

    regards,

    Charles