• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 32 subscribers
  • Views 417 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DMA Transfer Measurement

Steeve Bernier
Prodigy 20 points

Hi guys,

I am currently using two DMA to send data to an external device. The first DMA is preparing the data and the second is sending it.

The first DMA is taking an input buffer and it is formatting the data as follow. In fact the buffer has 1000 bytes.

A B C D E F

to

A  X B  X C  X D  X E  X F  X

1) X is a Don't care
2) One cell is a byte
3) Block Transfer
4) Read and Write size is 8 bits

The second DMA is taking the structure generated by the first one and it is sending it to the external device.

1) Block Transfer
2) Read and Write size is 16 bits

When I measure the time between the DMA start and the BTCA interrupt, the first DMA gives me 155.2 us and the second gives 118.0 us. I am trying to understand the difference of 37.2 us since it the same data (1000 times 8 bits vs 1000 times 16 bits).

Any idea ?

Thanks,

Steeve

  • 0
    TI__Genius 13810 points

    Steeve,

    We received your post and will get back to you soon.

    Regards,

    Haixiao

  • 0
    TI__Genius 13810 points

    Can you describe the source location and destination location of those two DMA transfers?

    DMA transfer between different memories takes different time. For example, a DMA from EMIF will take much longer than transfer in MCU internal SRAM.

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    Prodigy 20 points

    Hi, Both transferts are from internal SRAM to internal SRAM. It is the reason why I don't understand the gap. Thanks,

  • 0 in reply to Steeve Bernier
    TI__Guru 69070 points

    Steeve,

    Could it be something as simple as this.  After you setup the first DMA transfer and it starts, you are still using the CPU actively to setup the 2nd DMA transfer.  This means the CPU is probably also accessing the SRAM and maybe arbitrating against the DMA for SRAM accesses slowing down the DMA.  After the 2nd DMA is configured, do you do something like put the CPU in a while() loop where it's not really accessing SRAM?  Then the DMA may be able to get it's job done faster not having to aribtrate against the CPU.

    Just a thought - if this sounds like it might fit then there could be some experiments to confirm.