ADC1 / ADC2 Differing Conversion Results for Shared Input Channel

Tony,

From the picture, I see a constant 5 lsb difference between ADC core 1 and core 2. I don't understand either. I will forward it to our ADC expert.

Thanks,

Haixiao

Hi,

I should also point out that both ADCs have been calibrated and come up with a small offset value (1), so I guess they are reading the reference voltage at the same value.

Any thoughts yet?

Regards, Tony.

Hi,

This must be a tricky one. Are you able to replicate my findings?

Regards, Tony

Hi Tony,

Sorry for losing track of this post. We are investigating possible leakage paths through the shared input switches that could explain this observation, and will post an answer soon.

In the mean while, could you repeat your experiment with an increased sampling time? It would be interesting to see if this affects the delta between the conversion results of the two ADCs in this case.

Regards, Sunil

Hi Sunil,

Are you able to replicate my findings?

Regards, Tony

Hi Sunil,

Attached are 200ns and 500ns sample times. There does not appear to be a difference in readings. We use 200ns in our application as we don't achieve any greater accuracy with longer sample times. The discharge time is 50ns which I am informed in another post is sufficient. Indeed, in my own experiment, increasing the discharge time to 200ns makes no difference.

200ns

500ns

Regards, Tony

Hi Tony,

Can you please upload a picture of the circuit driving the shared input?

Regards, Sunil

I will email you the schematic if you give me your email address. This is subject to our NDA.

Hi Tony,

I have sent you a "friend request" that will allow you to share information with me without having to disclose it on the public forum.

Regards, Sunil

Hi Sunil,

Thanks for the update. I am confused by the recommended workaround in your attachment:

"It is not recommended to allow the two ADCs to operate asynchronously to each other. The timings when each ADC is sampling its input needs to be carefully managed such that they do not overlap."

Surely the problem arises when the channels are sampled at the same time, i.e. synchronously?

Regards,

Tony.

Hi Tony,

By "asynchronous" I meant that the sampling windows of the two ADCs cannot be completely independent now. The application designer must make sure that the two ADCs do not sample at the same time, or that the sampling windows do not overlap.

One more thing: this issue appears only when current is being injected into a shared channel as shown in the document.

Regards, Sunil

Hi Sunil,

Okay, I see, but others may misunderstand as I did.

In summary, are you saying:

1. A shared ADC channel should not be sampled at the same time as any other ADC channel as the other channel's results will be offset. The shared ADC channel results will not be offset.
2. Unique ADC channels can be sampled at the same time as other unique ADC channels with no impact (offset).

Regards, Tony.

Hi Tony,

Yes, that is correct. We will ensure that the errata document states the behavior and suggested workaround clearly.

Regards, Sunil

Hi Sunil,

This has a major impact on our design as we require to sample at two couples of ADC channels for which the two channels in the couple must be sampled at the same time. This is not a very unusual requirement, and is one of the main reasons for having two ADC modules. The two couples, so four channels would ideally all be sampled at the same time but a compromise we have already made is to split them into two groups so that there is only a 1 us difference across sample times. To sample these four channels on unique channels would increase the time between samples to 3 us.

I wonder if you have any idea when this flaw will be addressed in the silicon?

Regards, Tony.

Hi Tony,

The parasitic (leakage) current through the PMOS switches is significantly worse when one side of the switch is grounded (via 220 ohm in the figure 1 of document) while the other side is at VDDA (3.3V or 5V). This leakage should reduce exponentially if channel B in the figure is at some voltage < VDDA - 0.3V.

This may be a better "workaround" in some applications, depending on the input levels being sampled. 

Regards, Sunil

Hi Sunil,

So, is there any idea about when this problem might be fixed in silicon?

Regards, Tony.

Hi Tony,

The feasibility of a silicon update is being evaluated. I will update the post once any decision has been made.

Regards, Sunil

Hi Sunil,

I have investigated this effect and can see it myself. I am now thinking about how I might 'tune' it out, as it were.

Considering a unique channel sampled at the same time as a shared channel:

From what I can see, the degree of offset at the unique channel is directly proportional to the voltage at the shared channel. I think that I can therefore apply a tuned offset to the unique channel reading which is a proportion of the shared channel reading.

Question 1: Do you think that the offset (i.e. effect) will be the same for all combinations of unique/shared channel pairs? Personally, I would have thought that this is the case. If the offset is the same across all channels, then I only need to have one tune across all channels. UPDATE: Thinking about it, the offset will depend on the nature of my external circuit and so I will need to tune each unique/shared channel pair that I use according to my architecture. Do you agree? Other questions below still apply!

Question 2: Do you think that the offset will be the same for all devices in a particular family (so within all TMS570LS2124 for example)? Again, I would have thought that this is the case. If the offset is the same across all devices, then I only need to have one tune across all devices.

Considering a shared channel sampled at the same time as another shared channel:

Question 3: Presumably each shared channel read would affect the other, so both readings would be offset by some degree?

Regards, Tony.

Hello,

Is there any news of when a silicon fix will be available for this problem? Having to perform workarounds to get an accurate reading from an ADC is not something I would expect to have to do.

Regards,
Richard

Hi Richard,

A fix for this issue requires a significant change to the dual-input switch, and is not planned for the current Hercules MCUs.

Regards, Sunil